VSC6134
Datasheet
3.13.2
Global MPU Register 1 - Status Register and Counter Clear Control
Address:
0x001
Register Reset Value:
0xC000
Table 399. Global MPU Register 1 - Status Register and Counter Clear Control
Reset
Value
Bit
Name
Access
Description
15
CLR_RD_WRN
R/W
Configuration bit used to indicate whether the status
registers are cleared after a read or after a write.
0: Clear-on-write. In this mode, the read of a register
is optionally followed by a write to clear individual
bits (bits which have a 1 written to them are cleared).
1: Clear-on-read. In this mode, reading a register
clears all of the bits which were set before the read
occured.
1
14
SAT_ROLLOVERN
R/W
Configuration bit used to indicate whether the
counters are allowed to saturate or rollover. Except
for 10GE counters use XGE_SAT_ROLLOVERN bit
instead.
1
0: Rollover. Counters roll over once they reach the
maximum value. In this mode, counters are not
cleared on read.
1: Saturate. Counters remain at the saturated value
once they reach the maximum value. In this mode,
counters are cleared on read.
13:0
Reserved
RO
0x0000
365 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
