VSC6134
Datasheet
3.13.5
Global MPU Register 4 - One-Second Pulse LSW Count
Address:
0x004
Register Reset Value:
0xB0F8
Table 402. Global MPU Register 4 - One-Second Pulse LSW Count
Reset
Value
Bit
Name
Access
Description
15:0
SECONDP_CNT[15:0]
R/W
The 16 LSW bits of the internal one-second pulse
counter. The value to be programmed depends on
the selected clock domain (see “Performance
Monitor One-Second Pulse,’ page 195). This register
should be set to 0x8600 to generate a one-second
pulse when SONET clock is selected by
0xB0F8
SECP_CLK_SEL[3:0].
3.13.6
Global MPU Register 5 - One-Second Pulse Clock and Source Control
Address:
0x005
Register Reset Value:
0x0800
Table 403. Global MPU Register 5 - One-Second Pulse Clock and Source Control
Reset
Value
Bit
Name
Access
Description
15:12
SECP_CLK_SEL[3:0]
R/W
One of four clock domains can be selected and
divided down to generate the one-second pulse.
1000: Add path client clock is selected (155 MHz in
SDH mode)
0000
0100: Drop path client clock is selected (155 MHz in
SDH mode)
0010: Add path line clock is selected (167 MHz in
EFEC mode)
0001: Drop path line clock is selected (167 MHz in
EFEC mode)
0000: No clock is selected
others - Reserved
11
SECP_SOURCE_SEL
Reserved
R/W
RO
0: Software mode is selected for generating the
one-second pulse.
1: Internal automatic generation mode is selected for
the one-second pulse.
1
10:0
0x000
367 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
