VSC6134
Datasheet
3.3.15
BER Monitor Signal Fail Clear Threshold (LSW) Register
Address:
0xC6D: Add Path
0x46D: Drop Path
0x1EC3
Register Reset Value:
Table 124. BER Monitor Signal Fail Clear Threshold (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
SF_CLR_THRESH[15:0]
R/W
Lower portion of the SF_CLR_THRESH register.
The value is ignored for the rate detection algorithm
CNT_CLR_CTRL =’1’.
0x1EC3
3.3.16
BER Monitor Signal Fail Error Decrement Register
Address:
0xC6E: Add Path
0x46E: Drop Path
0x1EC3
Register Reset Value:
Table 125. BER Monitor Signal Fail Error Decrement Register
Reset
Value
Bit
15
Name
Access
RO
Description
Reserved
0
14:0
SF_ERR_DEC[14:0]
R/W
Signal Fail Error Decrement register. The value is ignored
for the rate detection algorithm CNT_CLR_CTRL =’1’.
0x1EC3
3.3.17
J0 Monitor Valid Message Registers
Address:
0xC80 to 0xC9F: Add Path
0x480 to 0x49F: Drop Path
0x0000
Register Reset Value:
Table 126. J0 Monitor Valid Message Registers
Reset
Value
Bit
15:8
7:0
Name
Access
R/W
Description
J0BYTEm[15:8]
J0BYTEm[7:0]
J0 byte number 2m, where m = 0 to 31
J0 byte number (2m+1), where m = 0 to 31
0x00
0x00
R/W
238 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
