VSC6134
Datasheet
3.3.6
BER Monitor Signal Degrade Error Threshold (LSW) Register
Address:
0xC64: Add Path
0x464: Drop Path
0x0312
Register Reset Value:
Table 115. BER Monitor Signal Degrade Error Threshold (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
SD_ERR_THRESH[15:0]
R/W
Lower portion of the Signal Degrade Error Threshold
register
0x0312
3.3.7
BER Monitor Signal Degrade Clear Threshold (MSW) Register
Address:
0xC65: Add Path
0x465: Drop Path
0x0000
Register Reset Value:
Table 116. BER Monitor Signal Degrade Clear Threshold (MSW) Register
Reset
Value
Bit
15:3
2:0
Name
Access
RO
Description
Reserved
0x000
0x0
SD_CLR_THRESH[18:16]
R/W
Upper portion of the Signal Degrade Clear Threshold
register
3.3.8
BER Monitor Signal Degrade Clear Threshold (LSW) Register
Address:
0xC66: Add Path
0x466: Drop Path
0x004D
Register Reset Value:
Table 117. BER Monitor Signal Degrade Clear Threshold (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
SD_CLR_THRESH[15:0]
R/W
Lower portion of the Signal Degrade Clear Threshold
register. The value is ignored for the rate detection
algorithm CNT_CLR_CTRL =’1’.
0x004D
235 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
