VSC6134
Datasheet
3.3.19
TIM Control Register
Address:
0xCA1: Add Path
0x4A1: Drop Path
0x0000
Register Reset Value:
Table 128. TIM Control Register
Reset
Value
Bit
Name
Access
Description
15
TIM_CTRL
R/W
TIM output control.
0
1: TIM output to be connected to the TIM_FORCE register.
0: TIM output controlled by J0 monitor. For normal
operation.
14
TIM_FORCE
R/W
Forcing the value of the TIM output.
0
3.3.20
SOH Monitor DCC Message Registers
Address:
0xCC0 to 0xCE3: Add Path
0x4C0 to 0x4E3: Drop Path
0x0000
Register Reset Value:
Table 129. SOH Monitor DCC Message Registers
Reset
Value
Bit
Name
Access
Description
15:0
SDCCBYTEn[15:0]
RO
Section DCC bytes accumulated for 24 consecutive
frames.The bytes are stored in the memory in the order
they are received, that is,
0x0000
SDCCBYTE0[15:8] - D1, SDCCBYTE0[7:0] - D2,
SDCCBYTE1[15:8] - D3, SDCCBYTE1[7:0] - D1,
SDCCBYTE2[15:8] - D2, SDCCBYTE2[7:0] - D3,
SDCCBYTE3[15:8] - D1, SDCCBYTE3[7:0] - D2,
...
SDCCBYTEn[15:8] - D2, SDCCBYTEn[7:0] - D3,
and so forth, where n = (0 to 35)
240 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
