VSC6134
Datasheet
3.3.22
SOH Monitor Interrupt Status Register
Address:
0xCF1: Add Path
0x4F1: Drop Path
0x0000
Register Reset Value:
Table 131. SOH Monitor Interrupt Status Register
Reset
Value
Bit
Name
Access
Description
15
SDCCRDYS
R/W
Section DCC status bit. The bit is set when
DCC (D1-D3) bytes are extracted for 24 consecutive
frames.
0
14
13
J0S
R/W
R/W
Change of state for J0 message status bit. Active, when a
new J0 message is validated or a J0 mismatch is detected.
0
0
SFS
Signal fail status bit. The bit is set, when the number of B1
or B2 BIP errors exceeds or drops below the signal fail
thresholds.
12
SDS
R/W
Signal degrade status bit. The bit is set, when the number
of B1 or B2 BIP errors exceeds or drops below the signal
degrade thresholds.
0
11
10
9
BIPERRS
E1F1RDYS
RS_AISS
R/W
R/W
R/W
B1 BIP-8 error status bit. The status is set when a B1 error
is detected.
0
0
0
New E1 and F1 bytes status bits. This bit is set for every
frame, when new E1 and F1 bytes are received.
RS_AIS_L status bits. The bit is set when the
RS_AIS_L state is detected or removed.
8:7
6
Reserved
J0L
RO
RO
0
0
J0 message current state (live). Active high, when the
J0 trace is valid.
5
4
3
SFL
RO
RO
RO
Signal fail current state (live). Active high, when the signal
fail alarm is active.
0
0
0
SDL
Signal degrade current state (live). Active high, when the
signal degrade alarm is active.
RS_AISL
RS_AIS current state (live). Active high, when the J0 byte is
0xFF for 3 or 5 consecutive frames and LOHM_AIS_L is
active high.
2:0
Reserved
RO
0
242 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
