VSC6134
Datasheet
3.3.21
SOH Monitor Interrupt Mask Register
Address:
0xCF0: Add Path
0x4F0: Drop Path
0xFE00
Register Reset Value:
Table 130. SOH Monitor Interrupt Mask Register
Reset
Value
Bit
Name
Access
Description
15
SDCCRDYM
R/W
Mask for the section DCC interrupt.
1: Mask interrupt.
1
0: Allow RX_DCCRDYS to generate the interrupt.
14
13
12
11
10
9
J0M
R/W
R/W
R/W
R/W
R/W
R/W
RO
Mask for the J0 change of state interrupt.
1: Mask interrupt.
0: Allow J0S to generate the interrupt.
1
SFM
Mask for the signal fail alarm interrupt.
1: Mask interrupt.
0: Allow SFS to generate the interrupt.
1
1
SDM
Mask for the signal degrade alarm interrupt.
1: Mask interrupt.
0: Allow SDS to generate the interrupt.
BIPERRM
E1F1RDYM
RS_AISM
Reserved
Mask for the B1 BIP-8 error interrupt.
1: Mask interrupt.
0: Allow BIPERRS to generate the interrupt.
1
Mask for the new E1/F1 byte interrupt.
1: Mask interrupt.
0: Allow E1F1RDYS to generate the interrupt.
1
Mask for the RS_AIS_L alarm interrupt.
1: Mask interrupt.
0: Allow RS_AISS to generate the interrupt.
1
8:0
0x00
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
