VSC6134
Datasheet
3.3.3
BER Monitor Signal Degrade Monitored Frames (MSW) Register
Address:
0xC61: Add Path
0x461: Drop Path
0x0000
Register Reset Value:
Table 112. BER Monitor Signal Degrade Monitored Frames (MSW) Register
Reset
Value
Bit
15:4
3:0
Name
Access
RO
Description
Reserved
0x000
0x0
SD_FRAME[19:16]
R/W
Upper portion of the SD_FRAME register. To access a
20-bit register, two consecutive read/write cycles are
required. The first cycle accesses this MSW [19:16], and
the second cycle accesses the LSW [15:0] (Table 113).
3.3.4
BER Monitor Signal Degrade Monitored Frames (LSW) Register
Address:
0xC62: Add Path
0x462: Drop Path
0x0040
Register Reset Value:
Table 113. BER Monitor Signal Degrade Monitored Frames (LSW) Register
Reset
Value
Bit
Name
Access
Description
15:0
SD_FRAME[15:0]
R/W
Lower portion of the SD_FRAME register. To access a
20-bit register, two consecutive read/write cycles are
required. The first cycle accesses MSW [19:16]
(Table 112), and the second cycle accesses this LSW
[15:0].
0x0040
3.3.5
BER Monitor Signal Degrade Error Threshold (MSW) Register
Address:
0xC63: Add Path
0x463: Drop Path
0x0000
Register Reset Value:
Table 114. BER Monitor Signal Degrade Error Threshold (MSW) Register
Reset
Value
Bit
15:3
2:0
Name
Access
RO
Description
Reserved
0x000
0x0
SD_ERR_THRESH[18:16]
R/W
Upper portion of the Signal Degrade Error Threshold
register
234 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
