VSC6134
Datasheet
4.2.13 Intel Synchronous Mode—Read Cycle ................................................................. 401
4.2.14 Intel Synchronous Mode—Write Cycle.................................................................. 402
4.2.15 Intel Asynchronous Mode—Read Cycle................................................................ 403
4.2.16 Intel Asynchronous Mode—Write Cycle................................................................ 404
Operating Conditions .......................................................................................................... 405
Stress Ratings..................................................................................................................... 405
Power Supply Dissipation Requirements............................................................................ 406
4.3
4.4
4.5
5
Pin Descriptions............................................................................................................................. 407
5.1 Pin Identifications................................................................................................................ 407
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
Microprocessor Interface Pins............................................................................... 407
Line Rx Interface Pins ........................................................................................... 410
Line Tx Interface Pins............................................................................................ 411
Client Rx Interface Pins......................................................................................... 412
Client Tx Interface Pins ......................................................................................... 414
Serial OTU DW Overhead FPGA Interface Pins................................................... 415
Serial SONET/SDH Overhead FPGA Interface Pins............................................. 416
VCXO Interface Pins ............................................................................................. 417
RLL Interface Pins................................................................................................. 418
5.1.10 JTAG Interface Pins .............................................................................................. 418
5.1.11 Scan Test Pins ...................................................................................................... 418
5.1.12 LVDS I/O Test Pins ............................................................................................... 422
5.1.13 Power Supply Pins ................................................................................................ 423
6
7
Package Information...................................................................................................................... 429
6.1
6.2
6.3
Package Drawing................................................................................................................ 429
Thermal Specifications........................................................................................................ 431
Moisture Sensitivity ............................................................................................................. 431
Design Considerations.................................................................................................................. 433
7.1
SONET Monitor and Generator........................................................................................... 433
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
J0 Monitor 16-Byte Mode ...................................................................................... 433
K2[2:0] Generator Using the MPU Interface and Overhead Insertion Port ........... 433
E2 Generator Using the Microprocessor Interface................................................ 433
Line DCC Generator Using the Microprocessor Interface..................................... 433
Section DCC Monitor and Generator Using the Microprocessor Interface............ 434
Z0 Generator Using the Microprocessor Interface ................................................ 434
Bit Error Rate Monitor Using the Leaky Bucket Algorithm..................................... 434
7.2
Digital Wrapper Overhead Processor ................................................................................. 434
7.2.1
7.2.2
Generic-AIS (Framed PN11)................................................................................. 434
GCC Monitor and Generator Using the MPU Interface and
Auto-Incrementation 435
7.2.3
SM/PM/TCM TTI Monitor and Generator Using the Microprocessor Interface ..... 435
Incoming Alignment Error (IAE) Interrupts ............................................................ 435
Framed PRBS Error Counter ................................................................................ 435
Asynchronous Mapping and De-Mapping ............................................................. 436
7.2.4
7.2.5
7.2.6
8
Ordering Information ..................................................................................................................... 437
14 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
