VSC6134
Datasheet
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
LOH Monitors I/O Description ................................................................................................49
SOH Monitors I/O Description................................................................................................55
Detection Times, Clearing Times, and Frame Times for Various BERs in OC-192...............57
Detection and Clearing Error Thresholds for Various BER in OC-192...................................58
Overhead Bytes to Be Inserted..............................................................................................62
SONET/SDH Overhead Insertion Block I/O...........................................................................62
LOH Generator I/O Signals....................................................................................................64
Line Overhead Generator Mode Functions............................................................................66
Line DCC Bytes......................................................................................................................68
SOH Generator Block I/O Description....................................................................................70
Section Overhead Generator Mode Functions.......................................................................72
TX DCC Register Arrangement..............................................................................................73
SDH/SONET Scrambler I/O Description................................................................................74
Rx Serial Overhead Interface Data Ordering .........................................................................75
SONET/SDH Overhead Extraction Block I/O.........................................................................76
Add Path Clock Crossing Buffer Modes.................................................................................81
Clock Crossing Block I/O Description ....................................................................................83
BIP8 Block I/O Description.....................................................................................................85
TXOCHD Input Overhead Content.........................................................................................86
ADD/DROP_FASCTRL Decoding..........................................................................................87
MFASCTRL Decoding............................................................................................................87
ADD/DROP_SMCTRL[1:0] Decoding ...................................................................................88
ADD/DROP_TCMCTRL[1:0] Decoding..................................................................................90
ADD/DROP_TP_RES Decoding for TCM ACT......................................................................91
ADD/DROP_PMCTRL[1:0] Decoding ....................................................................................92
ADD/DROP_APSCTRL Decoding .........................................................................................93
ADD/DROP_FTFLCTRL Decoding........................................................................................93
GCCx Interface Configuration................................................................................................94
EXP Generator Control ..........................................................................................................95
ODU RES Generator Control.................................................................................................95
ADD/DROP_PSICTRL Decoding...........................................................................................96
OPU RES Generator Control .................................................................................................97
ADD/DROP_TP_JB ...............................................................................................................97
Maintenance Block I/O Description........................................................................................98
Deinterleaving Buffer Block I/O Description.........................................................................100
RS Encoder Block I/O Description .......................................................................................101
Interleaving Buffer I/O Description .......................................................................................102
EFEC Encoder I/O Description ............................................................................................102
FEC Scrambler Block I/O Description..................................................................................103
FEC Error Generator Choices..............................................................................................104
Test Error Generator Block I/O Description .........................................................................104
Multiplexer Block I/O Description .........................................................................................105
FEC Descrambler Block I/O Description..............................................................................107
BCH Decoder Block I/O Description ....................................................................................107
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
17 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
