VSC6134
Datasheet
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
RS Decoder Pins..................................................................................................................111
Interleaving Buffer I/O Description .......................................................................................112
FEC Decoder Modes............................................................................................................113
Clock Crossing Buffer Modes...............................................................................................113
RXOCHD1 and RXOCHD0 Output Digital Wrapper Overhead Content..............................122
RXSTFD1 and RXSTFD0 Output Stuff Column Content .....................................................124
OTUk_TCM_INDEX[2:0] Encoding......................................................................................127
TCM STAT Field Decoding ..................................................................................................130
PM STAT Field Decoding.....................................................................................................132
ODUk_GCC_CFG[2:0] Decoding.........................................................................................134
Signal Fail Configuration......................................................................................................137
XGE_RX I/O Description......................................................................................................138
Framing Pattern for FRAMECTRL[1:0] ................................................................................141
Number of Correct Framing Patterns for INFRAME_CTRL[2:0] ..........................................142
Number of Errored Framing Patterns for OOF_CTRL[2:0] ..................................................142
Deserializer Block I/O Description........................................................................................146
Serializer Block I/O Description............................................................................................147
PRBS Generator Block I/O Description................................................................................149
PRBS Checker Block I/O Description ..................................................................................150
Operational Mode Descriptions............................................................................................152
External Microprocessor Interface Signals...........................................................................173
Microprocessor Interface Signals in the Motorola Pseudo-Synchronous Mode...................175
Microprocessor Interface Signals in the Motorola Synchronous Mode................................180
Microprocessor Interface Signals in the Intel Synchronous Mode .......................................183
Microprocessor Interface Signals in the Intel Asynchronous Mode .....................................186
Reset Block I/O Description .................................................................................................191
Input Clocks and Typical Frequencies .................................................................................192
Loss of Clock Monitor Block I/O Description........................................................................196
Global Registers...................................................................................................................201
Frame Aligner Registers ......................................................................................................202
Drop 10 G Ethernet Monitor Registers.................................................................................203
Drop FEC Decoder Registers ..............................................................................................206
Drop FEC Encoder Registers...............................................................................................207
Drop PRBS Checker and Generator Registers....................................................................208
Drop FEC ASYNC Map Registers........................................................................................208
Drop SONET Section Overhead Monitor Registers.............................................................208
Drop SONET/SDH Frame Aligner Registers........................................................................209
Drop SONET Line Overhead Monitor Registers ..................................................................210
Drop SONET Section Overhead Generator Registers.........................................................210
Drop DW Overhead Processor/FEC Performance Monitor Registers .................................211
Drop SONET Line Overhead Generator Registers..............................................................214
Add FEC Encoder Registers................................................................................................214
Add FEC Decoder Registers................................................................................................216
Add PRBS Generator and Checker Registers .....................................................................216
Add 10 G Ethernet Monitor Registers ..................................................................................216
Add SONET Section Overhead Monitor Registers ..............................................................219
Add SONET Frame Aligner Registers..................................................................................220
Add FEC Frame Aligner Registers.......................................................................................221
Add Line Overhead Monitor Registers.................................................................................221
Add Section Overhead Generator Registers........................................................................222
Add DW Overhead Processor/FEC Performance Monitor Registers...................................222
18 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
