VSC6134
Datasheet
3.8.48 DW Tandem Connection Monitor TTI FIFO Access Register ............................... 307
3.8.49 DW Tandem Connection Monitor Configuration Register ..................................... 307
3.8.50 DW Tandem Connection Monitor BIP-8 Bit Error Count Register (MSW)............. 308
3.8.51 DW Tandem Connection Monitor BIP-8 Bit Error Count Register (LSW).............. 308
3.8.52 DW Tandem Connection Monitor BIP-8 Block Error Count Register (MSW) ........ 309
3.8.53 DW Tandem Connection Monitor BIP-8 Block Error Count Register (LSW) ......... 309
3.8.54 DW Tandem Connection Monitor BEI Count Register (MSW).............................. 309
3.8.55 DW Tandem Connection Monitor BEI Count Register (LSW)............................... 310
3.8.56 DW Path Monitor TTI FIFO Access Register ........................................................ 310
3.8.57 DW Path Monitor Configuration Register .............................................................. 311
3.8.58 DW Path Monitor BIP-8 Bit Error Count Register (MSW)...................................... 311
3.8.59 DW Path Monitor BIP-8 Bit Error Count Register (LSW)....................................... 311
3.8.60 DW Path Monitor BIP-8 Block Error Count Register (MSW)................................. 312
3.8.61 DW Path Monitor BIP-8 Block Error Count Register (LSW).................................. 312
3.8.62 DW Path Monitor BEI Count Register (MSW)....................................................... 312
3.8.63 DW Path Monitor BEI Count Register (LSW)........................................................ 313
3.8.64 Enhanced FEC Total Corrected Bit Error Count (LSW) ........................................ 313
3.8.65 Enhanced FEC Total Corrected Bit Error Count (MSW) ....................................... 313
3.8.66 Enhanced FEC 1 Uncorrectable Code Word Count (LSW)................................... 313
3.8.67 Enhanced FEC 1 Uncorrectable Code Word Count (MSW).................................. 314
3.8.68 Enhanced FEC 2 Uncorrectable Code Word Count (LSW)................................... 314
3.8.69 Enhanced FEC 2 Uncorrectable Code Word Count (MSW).................................. 314
3.8.70 Enhanced FEC 3 Uncorrectable Code Word Count (LSW)................................... 314
3.8.71 Enhanced FEC 3 Uncorrectable Code Word Count (MSW).................................. 315
3.8.72 Enhanced FEC 4 Uncorrectable Code Word Count (LSW)................................... 315
3.8.73 Enhanced FEC 4 Uncorrectable Code Word Count (MSW).................................. 315
3.8.74 Enhanced FEC 1 Corrected Bit Error Count (LSW) .............................................. 315
3.8.75 Enhanced FEC 1 Corrected Bit Error Count (MSW) ............................................. 316
3.8.76 Enhanced FEC 2 Corrected Bit Error Count (LSW) .............................................. 316
3.8.77 Enhanced FEC 2 Corrected Bit Error Count (MSW) ............................................. 316
3.8.78 Enhanced FEC 3 Corrected Bit Error Count (LSW) .............................................. 316
3.8.79 Enhanced FEC 3 Corrected Bit Error Count (MSW) ............................................. 317
3.8.80 Enhanced FEC 4 Corrected Bit Error Count (LSW) .............................................. 317
3.8.81 Enhanced FEC 4 Corrected Bit Error Count (MSW) ............................................. 317
3.8.82 Standard FEC Corrected One Bit Error Count (LSW)........................................... 317
3.8.83 Standard FEC Corrected One Bit Error Count (MSW).......................................... 318
3.8.84 Standard FEC Corrected Zero Bit Error Count (LSW) .......................................... 318
3.8.85 Standard FEC Corrected Zero Bit Error Count (MSW) ......................................... 318
3.8.86 Enhanced FEC Corrected One Bit Error Count (LSW) ......................................... 319
3.8.87 Enhanced FEC Corrected One Bit Error Count (MSW) ........................................ 319
3.8.88 Enhanced FEC Corrected Zero Bit Error Count (LSW)......................................... 319
3.8.89 Enhanced FEC Corrected Zero Bit Error Count (MSW)........................................ 319
3.8.90 DW PSI Monitor Configuration Register................................................................ 320
3.8.91 DW PSI FIFO Access Register ............................................................................. 321
3.8.92 Framed PRBS Error Count Register (MSW)......................................................... 321
3.8.93 Framed PRBS Error Count Register (LSW).......................................................... 321
3.8.94 Framed PRBS Configuration Register .................................................................. 322
10 GbE Receiver Monitor Registers.................................................................................... 323
3.9
3.9.1
3.9.2
3.9.3
PCS Status Register ............................................................................................. 323
PCS Interrupt Mask Register................................................................................. 323
MIB/RMON Counters Saturate/Rollover Status Register 0................................... 324
10 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
