VSC6134
Datasheet
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Complete Device Bypass Mode .........................................................................................161
SONET Regenerator Mode ................................................................................................162
OTU Regenerator Mode Without FEC................................................................................163
SONET Regenerator Mode ................................................................................................164
LIC Test Line and Client Interface Loopback Modes..........................................................165
Client-Side Mid-Chip Loopback Mode................................................................................166
VSC6134 Mode Muxes Block Diagram ..............................................................................167
Detailed Block Diagram of Normal Mode ...........................................................................169
Protection Switching Using Two VSC6134 Devices in Normal Mode ................................170
Detailed Block Diagram for Protection Mode......................................................................171
Protection Switching Using Two VSC6134 Devices in Protection Mode............................172
Read Operation Sequence for Motorola Pseudo-Synchronous Interface ..........................176
Timing for a Read Operation of Pseudo-Synchronous Motorola Microprocessors ............177
Write Operation Sequence for Motorola Pseudo-Synchronous Interface...........................178
Timing for a Write Operation of Pseudo-Synchronous Motorola Microprocessors.............179
Read Operation Sequence for Motorola Synchronous Interface........................................180
Timing on Read Operation of Synchronous Motorola Microprocessors.............................181
Write Operation Sequence for Motorola Synchronous Interface........................................182
Timing for a Write Operation of Synchronous Motorola Microprocessors..........................182
Read Operation Sequence for Intel Synchronous Interface...............................................184
Timing for a Read Operation of Synchronous Intel Microprocessors.................................184
Write Operation Sequence for Intel Synchronous Interface ...............................................185
Timing for a Write Operation of Synchronous Intel Microprocessor...................................186
Read Operation Sequence for Intel Asynchronous Interface .............................................187
Timing for a Read Operation of Asynchronous Intel Microprocessors ...............................188
Write Operation Sequence for Intel Asynchronous Interface .............................................189
Timing for a Write Operation of Asynchronous Intel Microprocessor .................................190
Reset Generation Module...................................................................................................191
Clocking Structure ..............................................................................................................193
Interrupt Generation Scheme .............................................................................................194
Interrupt Generation and Clear Timing Example................................................................195
One-Second Pulse Source.................................................................................................195
TAP Controller Architecture................................................................................................198
16-Bit Word Swap Function................................................................................................199
Timing Diagram for LVDS Receive.....................................................................................391
Timing Diagram for LVDS Transmit....................................................................................391
Serial Interface Receive Data Timing.................................................................................393
Serial Interface Transmit Data Timing................................................................................394
Serial-Interface Receive Data Timing.................................................................................395
Serial-Interface Transmit Data Timing................................................................................396
Motorola Pseudo-Synchronous Mode—Read Cycle..........................................................397
Motorola Pseudo-Synchronous Mode—Write Cycle ..........................................................398
Motorola Synchronous Mode—Read Cycle .......................................................................399
Motorola Synchronous Mode—Write Cycle........................................................................400
Intel Synchronous Mode—Read Cycle...............................................................................401
Intel Synchronous Mode—Write Cycle...............................................................................402
Intel Asynchronous Mode—Read Cycle.............................................................................403
Intel Asynchronous Mode—Write Cycle.............................................................................404
Package Drawing ...............................................................................................................430
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
