VSC6134
Datasheet
Figures
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OTU Row Structure Using RS(255,239) Codes ...................................................................39
Interleaving (Encoding).........................................................................................................41
BCH-BCH Iterative Decoding Scheme.................................................................................42
BER Improvement Due to RS and EFEC Code ...................................................................43
VSC6134 High-Level Functional Block Diagram..................................................................45
Detailed Functional Block Diagram .....................................................................................46
Detailed Clocking Diagram...................................................................................................47
LOH Monitor Functional Block Diagram ...............................................................................48
SOH Monitor Functional Block Diagram...............................................................................54
Tx Overhead Insertion Port Timing.......................................................................................61
LOH Generator Functional Block Diagram...........................................................................66
Rx Serial Overhead Interface Timing ...................................................................................75
Rx Serial Overhead Interface Diagram.................................................................................77
Add Path FEC Encoder ........................................................................................................79
Drop Path FEC Encoder.......................................................................................................80
Transmit Digital Wrapper Overhead Serial Interface Timing................................................86
Layout of the GCC FIFO Buffer............................................................................................95
RS Encoder Block Diagram with the Data Inputs and Outputs ..........................................101
BCH Encoder Block Diagram .............................................................................................103
FEC Decoder Block............................................................................................................106
RS Decoder Block Diagram................................................................................................110
Rate Locked Loop Block and Its Connections....................................................................115
RLL Block Schematic .........................................................................................................116
RLL Implementation ...........................................................................................................117
Digital Wrapper Overhead..................................................................................................118
SM, PM, and TCM Subfields ..............................................................................................118
OPU Overhead...................................................................................................................119
Receive Digital Wrapper Overhead Serial Interface Timing...............................................122
Layout of the GCC FIFO Buffer..........................................................................................135
Frame Aligner Functional Block Diagram...........................................................................140
FSM State Machine for OOF..............................................................................................141
LOF State Machine.............................................................................................................143
Phase-Locked Loop Application Example..........................................................................145
Functional Diagram with PRBS Generators/Monitors ........................................................148
PRBS Checker Block Diagram...........................................................................................151
SONET/CBR10G to LFEC Mode........................................................................................153
10 GbE/Transparent to LFEC Mode...................................................................................154
StFEC to LFEC Bridge Without Payload Processing Mode ...............................................155
StFEC to LFEC Bridge with Payload Monitoring Mode ......................................................156
StFEC to LFEC Bridge with SONET Regeneration Mode..................................................157
StFEC to LFEC Bridge with SONET Regeneration and Asynchronous Remapping Mode 158
FEC from/to Legacy FEC Bridge with SONET Regeneration Mode...................................159
FEC from/to Legacy FEC Bridge with SONET Regeneration and Asynchronous Remapping
Mode160
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
