VSC6134
Datasheet
3.13.1 Global MPU Register 0 - Reset and Snapshot...................................................... 364
3.13.2 Global MPU Register 1 - Status Register and Counter Clear Control................... 365
3.13.3 Global MPU Register 2 - One-Second Pulse Software Control ............................ 366
3.13.4 Global MPU Register 3 - One-Second Pulse MSW Count.................................... 366
3.13.5 Global MPU Register 4 - One-Second Pulse LSW Count..................................... 367
3.13.6 Global MPU Register 5 - One-Second Pulse Clock and Source Control .............. 367
3.13.7 Global MPU Register 6 - Global Configuration Control 1...................................... 368
3.13.8 Global MPU Register 7 - Global Sync Status Mask .............................................. 369
3.13.9 Global MPU Register 8 - Global Sync Status........................................................ 370
3.13.10 Global MPU Register 9 - Device ID....................................................................... 371
3.13.11 Global MPU Register 10 - Device Version ............................................................ 371
3.13.12 Global MPU Register 11 - Scratch ........................................................................ 372
3.13.13 Global MPU Register 12 - Interface Control.......................................................... 372
3.13.14 Global MPU Register 13 - Block Interrupts ........................................................... 373
3.13.15 Global MPU Register 14 - Loss of Clock Mask ..................................................... 374
3.13.16 Global MPU Register 15 - Loss of Clock Interrupt Status ..................................... 375
3.13.17 Global MPU Register 16 - Global Configuration Control 2.................................... 376
3.13.18 Global MPU Register 17 - FEC Mode Register..................................................... 377
3.13.19 Global MPU Register 18 - Power-Down Register ................................................. 378
3.13.20 Global MPU Register 19 - Correction Register ..................................................... 379
3.13.21 Global MPU Register 20 - SerDes Control Register ............................................. 379
3.13.22 Global MPU Register 25 - Add SONET Enables................................................... 381
3.13.23 Global MPU Register 26 - Drop SONET Enables ................................................. 382
3.13.24 Global MPU Register 27 - Phase/Frequency Discriminator Register.................... 383
3.13.25 Global MPU Register 28 - Add PFD RX Clock Ratio Register.............................. 384
3.13.26 Global MPU Register 29 - Add PFD TX Clock Ratio Register .............................. 384
3.13.27 Global MPU Register 30 - Drop PFD RX Clock Ratio Register............................. 384
3.13.28 Global MPU Register 31 - Drop PFD TX Clock Ratio Register............................. 385
3.13.29 Global MPU Register 32 - SONET Block Interrupts.............................................. 385
3.13.30 Global MPU Register 33 - Global Client Interface Configuration Register 0......... 386
3.13.31 Global MPU Register 34 - Global Client Interface Configuration Register 1......... 386
3.13.32 Global MPU Register 35 - Block Interrupt Mask.................................................... 387
4
Electrical Specifications................................................................................................................ 389
4.1
DC Characteristics .............................................................................................................. 389
4.1.1
4.1.2
4.1.3
4.1.4
LVTTL Characteristics........................................................................................... 389
3.3 V LVTTL Driver Slew Rate .............................................................................. 389
LVDS Receiver Characteristics............................................................................. 390
LVDS Driver Characteristics.................................................................................. 390
4.2
AC Characteristics .............................................................................................................. 391
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
Data Input for LVDS Receive ................................................................................ 391
Data Output for LVDS Transmit ............................................................................ 391
Phase Frequency Discriminator ............................................................................ 392
Digital Wrapper Receive Interface (Overhead Extract) ......................................... 393
Digital Wrapper Transmit Interface (Overhead Insert) .......................................... 394
SONET/SDH Serial Interface—Receive Interface (Overhead Extract) ................. 395
SONET/SDH Serial Interface—Transmit Interface (Overhead Insert) .................. 396
Microprocessor Interface Characteristics.............................................................. 396
Motorola Pseudo-Synchronous Mode—Read Cycle............................................. 397
4.2.10 Motorola Pseudo-Synchronous—Write Cycle....................................................... 398
4.2.11 Motorola Synchronous Mode—Read Cycle .......................................................... 399
4.2.12 Motorola Synchronous Mode—Write Cycle .......................................................... 400
13 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
