VSC6134
Datasheet
The following functions are supported by the FEC encoder block:
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Clock domain crossing
Digital wrapper overhead generation and insertion
(255, 239) Reed Solomon encoding with 16-way byte interleaving
Enhanced FEC
Optional scrambling
Test error insertion
Test PRBS generation
Line FEC loopback
FEC encoder bypass (SDH/SONET or transparent pass through)
Substitution of fixed stuff all-zeros pattern instead of the FEC parity bytes in the OTUk frame when
the microprocessor configuration bit FEC_DISABLE is set. (This setting is used for working with
equipment supporting FEC with equipment not supporting FEC.)
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Alarm generation, which includes OTU AIS, generic AIS, ODU AIS, and OCI and LCK signaling.
The entire block runs on 167.3 MHz. It takes 510 cycles (64-bits per cycle) to transfer one G.975 (RS)
frame, which is, one OTUk row. It takes 1020 cycles to transfer one EFEC frame, which is, two OTUk
rows.
2.7.1
Add Path Clock Crossing Buffer
The clock crossing buffer consists of a 48-word × 64-bit two-port register array for passing data
between clock domains. Its various modes of operation are shown in Table 16, page 81. For more
information about the configuration bit settings and flow diagrams, see “Operational Modes,” page 152.
Table 16. Add Path Clock Crossing Buffer Modes
Configuration Bits
FEC_
MODE_E
ADD_FIFO_
MODE[1:0]
ADD_
STUFF_DIS
TRANSPARENT
_ADD
FEC_ENC_
BYPASS
ADD_
ASYNC
Mode
SDH /SONET to
SFEC (with OTUk
stuff bytes)
1
1
1
1
00
00
00
00
0
0
1
0
1
0
0
0
0
0
0
0
0
Transparent to
SFEC (with OTUk
stuff bytes)
0
1
1
SDH /SONET to
SFEC (without
OTUk stuff bytes)
Transparent to
SFEC (without
OTUk stuff bytes)
Add Path OTUk to
SFEC
1
1
11
01
x
x
x
x
0
0
0
0
Drop Path FEC to
SFEC
(regenerator
mode)
81 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
