VSC6134
Datasheet
2.4.2
2.4.3
B2 Generator and Error Insertion
The 192 B2 bytes of the outgoing STS-192/STM-64 frame are calculated and stored per frame for
placement into the 192 B2 bytes of the next frame (if TX_B2_SOURCE is 1). For testing purposes, it is
possible to introduce B2 errors by setting configuration bit TX_B2ERR_INSRT to 1 (this causes all 192
B2 bytes to be corrupted). The actual corruption is controlled using configuration mask register
TX_B2ERR_MSK[7:0]. Each corrupted B2 byte for insertion is simply the correct calculated B2 byte
XORed with TX_B2ERR_MSK[7:0].
K1 and K2 Generator
Configuration register TX_K1K2BYTE[15:0] is allocated for the user to program the K1 and K2 bytes.
These bytes are then inserted in the outgoing STS-192/STM-64 frame. TX_K1K2_INSRT and
TX_K2MD_INSRT control the insertion of the K1 and K2 bytes. TX_K1K2_INSRT controls the
insertion of TX_K1K2BYTE[15:3] into the K1 and K2 bytes of the outgoing SONET frame.
TX_K2MD_INSRT controls the insertion of TX_K1K2BYTE[2:0] into the least significant bits of the
K2 byte in the outgoing SONET frame. When either of these insertion controls is configured to 1, the
stored register values are inserted. When either insertion control is configured to 0, the K1 and K2 bytes
are passed through transparently.
Bits 2,1, and 0 of the K2 byte are used for remote defect indication signaling (RDI-L).
TX_K2MD_AUTO controls insertion of RDI-L (110) into the least significant bits of the K2 byte.
When TX_K2MD_INSRT is a 1, TX_K1K2BYTE[2:0] replaces the received K2[2:0] bits. RDI-L is
only inserted if any of the conditions that cause it are detected; otherwise, the input data or configuration
register data is transmitted in K2[2:0]. RDI-L is asserted for a minimum of 20 frames. If OP_AIS_L
(enable RDI_AIS_EN) is detected in the opposite data stream, RDI-L is returned if TX_K2MD_AUTO
is set. Maskable RDI-L conditions are signal fail OP_SF (enable RDI_SF_EN), loss-of-frame OP_LOF
(enable RDI_LOF_EN), loss-of-signal OP_LOS (enable RDI_LOS_EN), and regenerator section trace
identifier mismatch OP_TIM (enable RDI_TIM_EN).
2.4.4
Line DCC (D4-D12) Generator
The line (D4-D12) DCC bytes can be used as a 576-kbps data communication channel. The line DCC
bytes can be programmed for insertion using the microprocessor or the serial overhead interface. The
microprocessor can program up to 24 frames of line DCC bytes in configuration registers
TX_DCCXY[7:0]. The 24 frames of line DCC bytes are stored in a toggle buffer. This approach
eliminates possible contention between insertion and microprocessor updates of the line DCC
configuration registers. When the last address (0xFEB add path or 0x7EB drop path) of the line DCC
configuration registers is written, the insertion logic begins inserting from this buffer, leaving the other
buffer free for configuration. When the 24th frame of line DCC data (D12, frame 24) is inserted, an
interrupt status bit, TX_DCCRDY_S, is asserted. This interrupt status bit may be masked using mask bit
TX_DCCRDY_M.
The line DCC bytes can also be sourced from the serial overhead interface by setting the
TX_DCC_SOURCE configuration bit to 0, thereby passing the line DCC bytes through transparently.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
