VSC6134
Datasheet
Table 7.
LOH Generator I/O Signals (continued)
Name
Direction
Function
SP_AIS_L
SP_LOF
SP_LOS
SP_LOC
IN
IN
IN
IN
AIS line indication from the same path.
Loss-of-frame indication from the same path.
Loss-of-signal indication from the same path.
Loss-of-clock indication from the same path.
RDI-L Generation Signals
OP_AIS_L
OP_SF
IN
IN
IN
IN
IN
AIS line indication from the opposite path.
Signal fail indication from the opposite path.
Loss-of-frame indication from the opposite path.
Loss-of-signal indication from the opposite path.
OP_LOF
OP_LOS
OP_TIM_L
Regenerator section Trace-Identifier-Mismatch (J0) indication
from the opposite path.
Microprocessor Interface/Miscellaneous Signals
MPU_CLK
IN
Microprocessor clock used for accessing configuration and
status registers.
MPU_RESET_N
IN
Active low reset synchronous to the microprocessor clock. The
reset from the device pin (RESETN) and the software reset
register bit (SWRESETN) are combined and synchronized to
MPU_CLK. This is used for asynchronously initializing the
configuration registers.
MPU_LOHGEN_SEL
IN
LOH generator block select used for accessing configuration
and status registers.
MPU_RDENA
IN
IN
Microprocessor enable signal used for the read operation.
Microprocessor enable signal used for the write operation.
Microprocessor write input data bus.
MPU_WRENA
MPU_WDATA[15:0]
MPU_ADDR[15:0]
MPU_LOHGEN_RDATA [15:0]
MPU_LOHGEN_DTK
IN
IN
Microprocessor address bus.
OUT
OUT
Microprocessor read output data bus.
Microprocessor active high data acknowledgement signal (one
MPU_CLK clock pulse).
MPU_LOHGEN_INT
OUT
OUT
Microprocessor active high interrupt signal.
MPU_LOHGEN_INIT_DONE
Memory initialization indicator, synchronized to MPU_CLK.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
