VSC6134
Datasheet
The SOH Monitor block I/O is described in the following table.
Table 2.
SOH Monitors I/O Description
Name
Direction
Function
RESET_N
CLK
IN
IN
IN
Active low reset
155 MHz system clock
DATAI[63:0]
155 Mbps input data bus (before descrambling). DATAI is clocked in
on rising edge of CLK.
DATAI_DSCMBL[7:0]
IN
MSB slice of 155 Mbps input data bus (after descrambling).
DATAI_DSCMBL is clocked in on rising edge of CLK.
ROWCNT[3:0]
COLCNT[6:0]
SETCNT[4:0]
SYNCO
IN
IN
IN
IN
IN
IN
IN
IN
IN
Rx STS-192/STM-64 frame row counter (rows 0 to 8)
Rx STS-192/STM-64 frame column counter (columns 0 to 89)
Rx STS-192/STM-64 frame set counter (sets 0 to 23)
Frame sync
SEF
Active high severely-errored-frame alarm indicator.
Active high signal indicating loss-of-signal alarm.
Active high signal indicating loss-of-frame alarm.
Active high signal indicating AIS_L alarm.
LOS
LOF
LOHM_AIS_L
AIS_FRM_SEL
Select the number of consecutive frames for RS_AISL detection
(K1K2FRM configuration bit in LOHM).
CLOCK_1S
IN
IN
IN
IN
Performance Monitor one second pulse.
B2BITFRM_CNT[10:0]
B2ERRFRM_EN
CLR_RD_WRN
B2 bit error count per frame for BER monitor from LOHM
Active high enable signal. Mark the valid B2BITFRM_CNT.
Control signal indicating whether the status registers cleared
on-read or on-write.
MPU_CLK
IN
IN
Microprocessor clock
MPU_RESETN
MPU_RDENA
MPU_WRENA
MPU_ADDR[11:0]
MPU_WDATA[15:0]
Active low MPU_CLK reset.
Microprocessor read enable signal.
Microprocessor write enable signal.
Microprocessor address bus.
Microprocessor write data bus.
Microprocessor read data bus.
IN
IN
IN
IN
MPU_SOHM_RDATA
[15:0]
OUT
MPU_SOHM_DTK
MPU_SOHM_INT
OUT
OUT
IN
Microprocessor data acknowledgement pulse.
Microprocessor block interrupt.
MPU_SOHM_SEL
MPU_SAT_ROLLOVERN
Microprocessor block select for SOH monitor.
Control signal indicating whether the counters saturate or rollover.
IN
55 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
