VSC6134
Datasheet
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J0_PATTERN = 11: J0 monitoring is disabled.
The J0_REPEAT[2:0] bits define the number of repetitions needed to validate a new J0 message. The
number of repetitions range from 0 to 7. When J0_REPEAT[2:0] = 000, a new message is considered
valid after a complete J0 message is received following a mismatch.
The trace indicator mismatch (TIM) is indicated by the TIM output. When a mismatch occurs in the J0
message, the corresponding TIM bit is set to 1. The TIM output goes back to 0 only after a valid
message is received. The control bit TIM_CTRL allows the TIM output to be controlled by the
TIM_FORCE bit for testing purposes.
The J0 monitoring is disabled during LOS, LOF or SEF alarms, and internal frame counters are reset.
The block also monitors J0 byte for 0xFF value. If the value persists for 3 or 5 consecutive frames
(determined by the configuration bit K1K2FRM in LOHM) and the LOHM_AIS_L indication is
received from the line overhead monitor, the status bit RS_AISS is set, and a microprocessor interrupt
can be generated if the associated interrupt mask bit RS_AISM is 0. The current state of this alarm can
be observed through live bit RS_AISL. When either the AIS_L from LOH or the J0 byte is different for
the same number of consecutive frames, the RS_AISL live bit becomes inactive and the status bit
RS_AISS is set.
2.2.4
2.2.5
E1, F1 Monitor
The E1, F1 monitor block extracts the E1 byte (orderwire byte) and the F1 byte (user channel) for each
frame and then stores them in the registers E1BYTE[7:0] and F1BYTE[7:0], respectively. The status bit
E1F1RDYS is set and a microprocessor interrupt can be generated if the interrupt mask bit
E1F1RDYM = 0. The microprocessor then has a full frame to access bytes before a new update. The
E1/F1 extraction is disabled during LOS, LOF, or SEF alarms.
Section DCC Monitor (D1 to D3)
The bytes D1 to D3 are allocated in the first STS-1 of SONET/SDH frame for the line data
communication channel. A section DCC is one 192-Kbps [3 × 64] message-based channel for alarms,
maintenance, control, monitoring, administration, and other data communication needs between STE.
The monitor collects DCC bytes from 24 consecutive frames (3 ms), stores it in the memory
SDCCBYTE[36 × 16], and makes it available for the microprocessor. As soon as memory is updated,
the status bit SDCCRDYS is set, and a microprocessor interrupt is generated, if the interrupt mask bit
SDCCRDYM = 0. The system then has 3 ms to access memory, before it is overwritten with a new DCC
message, which significantly minimizes the number of microprocessor interrupts. Storage is
implemented as two ping-pong memory banks (two 36 × 16 register arrays). While bank A is getting
updated, bank B can be accessed by the microprocessor interface. After the new message is filled in
bank A, the banks are switched. Then bank A can be accessed by the microprocessor, and bank B is
ready for receiving new DCC bytes. Section DCC monitoring is disabled when any of the following
alarms are active: LOS, LOF, or SEF.
2.2.6
Z0 Extraction
The J0 byte and 191 Z0 bytes from each STS-192/STM-64 frame are extracted, stored in the memory
Z0BYTE[24 × 64], and made available to the system through the microprocessor interface. The Z0 byte
monitoring is disabled, when any of the following alarms are active: LOS, LOF, SEF.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
