VSC6134
Datasheet
byte contains an unused code or a code is irrelevant for the specific switching operation in three
consecutive frames. Because invalid code detection requires information not readily available to
hardware, it must be detected by the software from a validated K1 byte value. An inconsistent APS byte
defect occurs when no three consecutive K1 bytes of the last 12 successive frames are identical, starting
with the last frame that contains a previously consistent byte. The inconsistent K1 byte generates the
microprocessor interrupt K1INC_S if it is not masked by K1INC_M. The alarm is terminated if the
identical K1 byte values are received and are consistent for three consecutive frames. If the block is
configured to operate in 1+1 bidirectional mode (APSARC = 0 and APSDIR = 0 (default)), an
inconsistent K1 byte detection is disabled.
Block monitors for the three least significant bits [2:0] of K2 byte are used to detect the line alarm
indication signal (AIS_L: 111), line remote defect indication (RDI_L: 110), and bits [3:0] for APS
mode mismatch.
If AIS_L is detected in the number of consecutive frames set by K1K2FRM, an AIS state is declared
and the microprocessor interrupt signal is generated. Note that the number of consecutive frames is
programmed using the configuration register bit K1K2FRM (1 for 3 frames SDH and 0 for the default
value, which is 5 frames for SONET). The interrupt bit AIS_S and its associated interrupt mask bit
AIS_M, are used to indicate the change of AIS state (detect or remove) and generate interrupt. The
status bits are cleared on read or on write, depending on the global configuration bit CLR_RD_WRN (0
for clear on write; 1 for clear on read). The AIS defect is removed if any pattern other than 111 is
detected after the same number of consecutive frames (3 or 5).
Similarly, the line remote defect indication (RDI_L) defect is detected if a pattern 110 is observed
during the provisioned number of consecutive frames. The RDI defect state is then declared, and the
status bit RDI_S is asserted, creating a microprocessor interrupt (unless it is masked by RDI_M).
Removal of the RDI defect state takes place if any pattern other than 110 is received over the same
number of consecutive frames.
An APS mode mismatch defect is detected if the received bit 3 of the K2 byte differs from the
configured APSARC setting (0 if provisioned architecture is 1 + 1 (default), 1 for the 1:n mode) or
bits [2:0] differ from the provisioned settings. Configuration bit APSDIR selects between two direction
modes: 0 selects 101 if provisioned mode is bidirectional (default) and 1 selects 100 if configured to
unidirectional mode.
The mode mismatch is declared if any one of the following conditions is detected for the number of
consecutive frames set by K1K2FRM:
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Device configured for 1 + 1 protection switching (bit 3 of K2 byte 0), but it receives indication of
working in 1:n mode (bit 3 of K2 byte 1).
Device configured for 1:n mode (bit 3 of K2 byte 1), but it receives indication of working in 1 + 1
protection switching (bit 3 of K2 byte 0).
Device provisioned for bidirectional switching (bits [2:0] of K2 set to 101) but it receives indication
of working in unidirectional mode (bits [2:0] of K2 set to 100).
Device provisioned for unidirectional mode (bits [2:0] of K2 set to 100) but it receives indication of
working in bidirectional switching (bits [2:0] of K2 set to 101).
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
