VSC6134
Datasheet
2.2.2
Bit Error Rate (BER) Monitor
The BER monitor block detects the signal degrade (SD) and signal fail (SF) conditions if the number of
B1 or B2 BIP-8 errors exceed the programmed thresholds for the specified number of frames. Two
internal counters SDERR_CNT[18:0] and SFERR_CNT[18:0] count the number BIP-8 errors.
Depending on configuration bit B2B1N_SEL, the errors can be sourced either from B1(default) or B2
monitors. The block can be configured to monitor BER, using two distinct algorithms:
1. Leaky Bucket (CNT_CLR_CTRL = 0 default). For the leaky bucket algorithm, the total values of
the counters SDERR_CNT[18:0] and SFERR_CNT[18:0] are decremented by programmed values
SD_ERR_DEC[14:0] and SF_ERR_DEC[14:0] after the end of every monitored block (number of
SONET frames, programmed in SD_FRAME[19:0] or SF_FRAME[19:0]). Right before the values
of the counters are decremented, it is compared with corresponding error threshold values,
programmed in registers SD_ERR_THRESH[18:0] and SF_ERR_THRESH[18:0], respectively. If
the thresholds are reached or exceeded, the status bits SDS or SFS are set, indicating that the
monitored BER was exceeded. This condition creates a microprocessor interrupt if the interrupt
mask bits SDM or SFM are disabled (0). The SD or SF alarms are cleared, when the count values
drop below the clearing thresholds SD_CLR_THRESH[18:0] and SF_CLR_THRESH[18:0],
respectively, at the end of next monitored block. Clearing the SD and SF alarms also sets status bits
SDS or SFS, and creates a microprocessor interrupt signal if not masked by the SDM or SFM bits.
2. Rate Detection (CNT_CLR_CTRL = 1). For this method, the decrement values and clearing
thresholds are ignored, and the counts are cleared at the end of every monitored block that is
programmed in the SD_FRAME[19:0] and SF_FRAME[19:0] registers. If the number of BIP
errors reaches or exceeds the specified error thresholds, the status bits SDS or SFS are set, and a
microprocessor interrupt is generated if not masked by bits SDM or SFM. The SD and SF alarms
are cleared if the number of BIP errors in any of the monitored blocks does not reach the threshold
value.
The status bits are cleared on read or on write depending on the global configuration bit
CLR_RD_WRN (0 for clear on write, 1 for clear on read). The BER monitoring is disabled during the
LOS, LOF, or SEF alarms, and the internal frame counters are reset.
The following table shows the typical detection and clearing times for various BER conditions for
OC-192 data rates.
Table 3.
Detection Times, Clearing Times, and Frame Times for Various BERs in OC-192
Detection
Clearing
BER
10–3
10–4
10–5
10–6
10–7
10–8
10–9
Times
8 ms
Frames
64
Times
8 ms
Frames
64
8 ms
64
8 ms
64
8 ms
64
15.6 ms
156.25 ms
1.3 s
125
15.6 ms
156.25 ms
1.3 s
125
1250
10400
80000
640000
1250
10400
80000
10 s
10 s
80 s
57 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
