VSC6134
Datasheet
Codes other than 101 and 100 are ignored for purposes of monitoring for the APS mode mismatch
defect. The APS mode mismatch is neither detected nor terminated during AIS_L, LOS, LOF or SEF.
After APS mode mismatch detected, the microprocessor interrupt signal APSMM_S generated, if mask
bit APSMM_M is disabled. APS mode mismatch defect detection is disabled if equipment is configured
to operate in default mode (1+1 architecture APSARC = 0 and APSDIR = 0 bidirectional mode).
2.1.3
S1 Byte Synchronization Status Monitor
The S1 byte, which is located in the first STS-1 of STS-N, carries the synchronization status message
and provides synchronization quality measures of the transmission link in the least significant 4 bits.
The block recovers S1 byte from LOH, stores it in an 8-bit register S1BYTE[7:0], and checks for
persistency against previously stored value. If the new value of S1 byte repeats for at least
eight GR-253 R5-198) consecutive frames, a status bit S1NEW_S is set, and a microprocessor interrupt
is generated if the associated mask bit S1NEW_M = 0. The new value of S1 byte is updated in validated
register S1VALID[7:0] for the microprocessor to access. If 32 consecutive frames go by without
eight consecutive identical values, an inconsistent value indication is declared, status bit S1INC_S is set,
and the microprocessor interrupt is generated if not masked by the signal S1INC_M. The user may
configure the compare mode for S1 validation by provisioning the configuration bit S1COMP_MODE
(1 for validation based on the whole S1 byte value [7:0], 0 for the validation based only on the lower
nibble of the S1 byte [3:0] (default). This feature accommodates the future usage of upper nibble [7:4]
bits for synchronization purposes. The S1 byte monitoring is disabled during AIS_L, LOS, LOF or SEF
alarms, and all consistency counters are reset.
2.1.4
M0 and M1 Remote Error Indication Monitor
The remote error indication bytes M0 and M1 are located in the second and third STS-1 of STS-N and
represent the count of B2 bit errors detected in far-end LTE. The M0 and M1 bytes recovered from LOH
are stored in an internal 11-bit register, and the number of errors per second is accumulated in the 24-bit
counter M0M1ERRCNT[23:0]. For STS-192/STM-64, the maximum value of M0 and M1 errors cannot
exceed 1536 per frame and 12,288,000 per second. If the block receives a numerical value for the M0
and M1 bytes that is higher than the maximum value, the value of these bytes is ignored. After every
one-second pulse, the values of error counter are transferred to a cache register where they can be
accessed using the microprocessor interface within the next one-second period. The counter can be
cleared (using SAT_ROLLOVERN = 1) or set to retain its value (using SAT_ROLLOVERN = 0) as
soon as the transfer is completed. At the same time if any bit errors are received in the M0 and M1 bytes,
the status bit M0M1ERR_S is set, and the microprocessor interrupt is generated if mask bit
M0M1ERR_M = 0. During the time when LOS, LOF, SEF or AIS_L alarms are active, M0M1 count is
disabled.
To provide compatibility with older equipment that support single-byte REI_L in M1, configure the
block by setting the configuration bit M0_MODE to 1. In this mode, the maximum value of M1 cannot
exceed 255 errors per frame, and the value of the received M0 byte is ignored.
52 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
