VSC6134
Datasheet
Table 2.
SOH Monitors I/O Description (continued)
Name
Direction
Function
MPU_SOHM_INITDONE
OUT
Active high memory initialization complete indicator. After reset,
every memory block goes through an initialization sequence, and
the signal is asserted on completion.
RSOHMON_SF
RSOHMON_TIM
OUT
OUT
Signal fail alarm signal, passed to TX path in the opposite direction
for LOH generator RDI_L insertion.
Trace Identifier Mismatch alarm signal, passed to TX path in the
opposite direction for LOH generator RDI_L insertion.
B1BITFRM_CNT[3:0]
B1ERRFRM_EN
OUT
OUT
OUT
B1 bit error count per frame for the overhead extraction block
Active high enable signal. Mark the valid B1BITFRM_CNT.
SOHM_RSAIS_L
Active high RS_AIS_L alarm condition. The alarm is asserted if
0xFF is detected in the J0 byte for the programmed number of
consecutive frames (AIS_FRM_SEL is controlled by the
configuration bit K1K2FRM in LOHM), and AIS_L is detected by
LOHM.
2.2.1
B1 BIP-8 Monitor
The B1 BIP-8 monitor calculates the BIP-8 even parity over the entire bits of the scrambled
STM-64/STS-192 frame and compares that to the B1 byte received in the following frame. Two16-bit
internal counters, BIP8CNTIN[15:0] and BIP8CNTBLINT[15:0], keep the count of BIP-8 bit errors
and block errors, respectively. (For example, if calculated BIP-8 = 01011010 and received BIP-8 =
00011101, then the BIP8CNTIN[15:0] counter is incremented by 4 and the BIPBLKCNTINT[15:0] is
incremented by 1). Received B1 errors are accumulated within a one-second period, and the counts are
made available to the microprocessor. Every second the count of the BIP-8 parity errors and BIP-8 block
errors are transferred to a cache register BIP8CNT[15:0] and BIP8CNTBL[15:0] for microprocessor
read access. Depending on the microprocessor configuration bit SAT_ROLLOVERN, the internal
counters either clear (SAT_ROLLOVERN = 1) or retain their value (SAT_ROLLOVERN = 0) after the
counts are transferred. All BIP-8 errors are counted during the transfer.
After a B1 error is detected, the status bit BIPERRS and its associated interrupt mask bit, BIPERRM,
are used to indicate the BIP-8 error status and to generate interrupts. The status bit is cleared on read or
on write depending on the microprocessor configuration bit CLR_RD_WRN (0 for clear on write; 1 for
clear on read).
Error monitoring is disabled during the SEF, LOS, or LOF conditions.
The block also provides the number of B1 errors per frame to both the overhead extraction block for
external processing and to the BER monitor for generation of the signal degrade and signal fail alarms.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
