VSC6134
Datasheet
2.1.1
B2 BIP-8 Line Error Monitor
The B2 byte is allocated in each STS-1 frame for a line error monitoring function. Therefore, for
STS-192, there are 192 B2 bytes. Each B2 byte represent the result of a BIP-8 calculation over a single
STS-1, excluding its section overhead. The B2 BIP-8 monitor calculates even parity over all bits of the
line overhead and payload of unscrambled STM-64/STS-192 frame and compares that to the B2 bytes
received in the following frame. Resulting errors are accumulated within one second period and the
counts are made available to the microprocessor. Two internal counters, B2BITERRCNT[23:0] and
B2BLKERRCNT[20:0], keep count of all bit and block errors respectively. For the block error count,
one error is counted for each errored B2 byte; however, for the bit error count, one error is counted for
each bit within each B2 byte (maximum of eight errors are possible per B2 byte). For every one-second
pulse, the values of B2 bit and block error counters are transferred to associated cache registers where
they can be accessed using the microprocessor interface. The counters can be cleared
(SAT_ROLLOVERN = 1) or retain their value (SAT_ROLLOVERN = 0) after the count is read by the
microprocessor, depending on global configuration bit SAT_ROLLOVERN. All B2 errors are counted
during the transfer.
After a B2 error is detected, the status bit B2ERR_S is set, resulting in a microprocessor interrupt if the
associated interrupt mask bit B2ERR_M is disabled. The status bit can be cleared on read or cleared on
write, depending on global configuration bit CLR_RD_WRN (0- for clear on write; 1- for clear on
read). Error monitoring is disabled during SEF, LOS, LOF or AIS_L conditions.
The B2 BIP-8 block also counts the number of bit and block errors per frame in the separate counters
B2BITFRM_CNT[10:0] and B2BLKFRM_CNT[7:0]. The block passes the values to the line overhead
generator in the transmit direction for the insertion of the M0 and M1 (REI_L) bytes, to the overhead
extraction block for external processing, and to the BER monitor to generate signal degrade/signal fail
alarms. The output data is accompanied by the enable pulse B2ERRFRM_EN (one system clock cycle
wide). In the following cycle, the counter values are cleared. The maximum B2 error count per frame
cannot exceed 1536 bit errors and 192 block errors for STS-192/STM-64.
2.1.2
K1, K2 Automatic Protection Switching (APS) Monitor
The following features are supported by APS monitor:
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Validation of the received K1 and K2 bytes (persistency of new values for 3 consecutive frames)
Protection switching byte defect detection (inconsistent K1 byte for 12 consecutive frames)
Line AIS (AIS_L) detection (111 pattern in K2 byte [2:0] for 5 or 3 consecutive frames)
Line RDI (RDI_L) detection (110 pattern in K2 byte [2:0] for 5 or 3 consecutive frames)
APS mode mismatch defect (K2 byte [2:0] and bit [3] mismatch for 5 or 3 consecutive frames)
The block extracts the K1 and K2 bytes from LOH and stores it in a 16-bit register. If the received
values of the K1 and K2 bytes are different from the validated values and are consistent for a total of
three consecutive frames, a status bit K1K2NEW_S is set and a microprocessor interrupt is generated
when the mask bit K1K2NEW_M = 0. In this case, new values of the K1 and K2 bytes update the
validation register K1K2VALID ([15:8] for K1VALID and [7:0] for K2VALID), where it can be
accessed by the system using the microprocessor interface. Validation of the new K1 and K2 bytes and
alarm generation are not affected by the AIS_L status.
Based on Chapter 6.2.1.1.6.A of Telcordia GR-253, the protection switching byte defect occurs when
either invalid code or inconsistent APS byte is detected. An invalid code occurs when the incoming K1
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
