欢迎访问ic37.com |
会员登录 免费注册
发布采购

VSC6134ST-01 参数 Datasheet PDF下载

VSC6134ST-01图片预览
型号: VSC6134ST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
 浏览型号VSC6134ST-01的Datasheet PDF文件第45页浏览型号VSC6134ST-01的Datasheet PDF文件第46页浏览型号VSC6134ST-01的Datasheet PDF文件第47页浏览型号VSC6134ST-01的Datasheet PDF文件第48页浏览型号VSC6134ST-01的Datasheet PDF文件第50页浏览型号VSC6134ST-01的Datasheet PDF文件第51页浏览型号VSC6134ST-01的Datasheet PDF文件第52页浏览型号VSC6134ST-01的Datasheet PDF文件第53页  
VSC6134  
Datasheet  
The LOH monitor block I/O is described in the following table.  
Table 1.  
LOH Monitors I/O Description  
Name  
Direction  
Function  
RESET_N  
CLK  
IN  
IN  
IN  
Active low reset.  
155 MHz system clock.  
DATAI[63:0]  
155 Mbps input data bus (after descrambling). DATAI is clocked in on  
rising edge of CLK.  
ROWCNT[3:0]  
COLCNT[6:0]  
SETCNT[4:0]  
LOHM_EN  
IN  
IN  
IN  
IN  
Rx STS-192/STM-64 frame row counter (rows 0 to 8).  
Rx STS-192/STM-64 frame column counter (columns 0 to 89).  
Rx STS-192/STM-64 frame set counter (sets 0 to 23).  
Active high LOH monitor enable signal. If active, the data bus is  
disabled.  
SEF  
IN  
IN  
Active high severely-errored-frame alarm indicator.  
Active high signal indicating loss-of-signal alarm.  
Active high signal indicating loss-of-frame alarm.  
Performance monitor one-second clock.  
LOS  
LOF  
IN  
CLOCK_1S  
B2BITFRM_CNT[10:0]  
IN  
OUT  
B2 bit error count per frame for BER monitor in SOHM, M0,M1 bytes in  
the transmit path and overhead extraction block.  
B2BLKFRM_CNT[7:0]  
B2ERRFRM_EN  
OUT  
OUT  
B2 block error count per frame for overhead extraction block.  
Active high enable signal. Mark the valid B2BLKFRM_CNT and  
B2BITFRM_CNT.  
MPU_CLR_RD_WRN  
IN  
Control signal indicating whether the status registers are cleared on  
read or on write.  
MPU_CLK  
IN  
IN  
Microprocessor clock.  
MPU_RESETN  
Active low MPU_CLK reset.  
MPU_RDENA  
IN  
Microprocessor read enable signal.  
Microprocessor write enable signal.  
Microprocessor address bus.  
MPU_WRENA  
IN  
MPU_ADDR[15:0]  
MPU_WDATA[15:0]  
MPU_LOHM_RDATA[15:0]  
MPU_LOHM_DTK  
MPU_LOHM_INT  
MPU_LOHM_SEL  
MPU_SAT_ROLLOVERN  
MPU_LOHM_INITDONE  
IN  
IN  
Microprocessor write data bus.  
OUT  
OUT  
OUT  
IN  
Microprocessor read data bus.  
Microprocessor data acknowledgement pulse.  
Microprocessor block interrupt.  
Microprocessor block select for LOH monitor.  
Control signal indicating whether the counters saturate or rollover.  
IN  
OUT  
Active high memory initialization complete indicator. After reset, every  
memory block goes through an initialization sequence and the signal is  
asserted on completion.  
AIS_L_OUT  
OUT  
AIS_L alarm signal, passed to TX path in the same and opposite  
direction.  
49 of 438  
VMDS-10185 Revision 4.0  
July 2006  
 复制成功!