VSC6134
Datasheet
The following figure shows the VSC6134 detailed clocking diagram.
Figure 7. Detailed Clocking Diagram
VCO01
RXCLK0DIV
VCO10
TXCLK1
TXCLKSRC1
RXCLK1
LOCK
Monitor
VCOSRC1
Prescalar
Prescalar
rxclk_client_hslb
LOCK
Ser
f/4
Monitor
Des
LOCK
f/4
Monitor
txclk_client
rxclk_client
DROP
cli_txclk
ADD
dfe_txclk
rx_clk
DF_ENC
ck/3
ck/3
dropohclk1
drsdhohclk
agap_clk
clock-xing
R/S
degap_clk
dsdh_txclk
SDH
AF_DEC
afd_txclk
cli_txclk
clock logic
deth_txclk
clock logic
aeth_clk
line_rxclk
XGE_RX
clk_156
asdh_clk
SDH
d90clk
d90clk
ck/90
XGE_RX
clk_156
ck gap
MPU
dgap_clk
ck gap
ck/90
clk_sdhpe
efec_rxclk
clock-xing
clock-xing
agap_clk
DF_DEC
EFEC
rxclk1div
clock-xing
i_mpclk
AF_ENC
ck/3
rsfec_rxclk
R/S
ck/3
dropohck0
tx_clk
fec_rxclk
txclk_line
rxclk_line
LOCK
f/4
Monitor
f/4
Ser
Des
rxclk_line_hslb
LOCK
Monitor
Prescalar
Prescalar
TXCLKSRC0 TXCLK0
RXCLK0
MPCLK
RXCLK1DIV
VCO00
47 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
