VSC6134
Datasheet
The live bits OTUk_SM_TTISAPIL (SAPI), OTUk_SM_TTIDAPIL (DAPI), and
OTUk_SM_TTIOPSL (operator-specific) indicate whether the respective TTI fields stored in the stack
are valid (1) or invalid (0). A change of any field state sets the respective status bit
OTUk_SM_TTISAPIS (SAPI), OTUk_SM_TTIDAPIS (DAPI), or OTUk_SM_TTIOPSS
(operator-specific). The status bits with their respective interrupt mask bits OTUk_SM_TTISAPIM
(SAPI), OTUk_SM_TTIDAPIM (DAPI), and OTUk_SM_TTIOPSM (operator-specific) create
maskable hardware interrupts.
A TTI trace is valid after n consecutive matches (that is, debounced n times), where n has a value of
1 through 8 and is set through register bits OTUk_TTI_MAT[2:0]. A TTI trace is invalid after
m consecutive mismatches, where m has a value of 1 through 8 and is set through register bits
OTUk_TTI_MIS[2:0].
Any one of the following conditions resets the debouncing and pauses SM TTI monitoring:
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OOF when OTUk_OOFDBC_CTRL = 1
LOF
LOS
LOM
A zero-to-one transition on OTUk_SM_TTIINVD invalidates the entire TTI trace.
SM Bit Interleaved Parity 8 (BIP-8) Monitor
Two internal counters accumulate the BIP-8 parity errors (24-bit counter) and BIP-8 block errors (20-bit
counter). If calculated BIP-8 is 01011010 and received BIP-8 is 00011101, for example, then the parity
error counter increments by 4 and the block error counter increments by 1.
Once every second, the SM BIP-8 error counts transfer to a set of duplicate cache registers
OTUk_SM_BIP8CNT[23:0] and OTUk_SM_BIP8CNTBL[19:0] for microprocessor read access.
Depending on the microprocessor configuration bit SAT_ROLLOVERN, the accumulators either clear
(SAT_ROLLOVERN = 1) or retain their value (SAT_ROLLOVERN = 0) when the count transfers.
Any one of the following conditions pauses SM BIP-8 monitoring:
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OOF when OTUk_OOFCNT_CTRL = 1
LOF
LOS
SM IAE when OTUk_IAE_CTRL = 1
A BIP-8 parity error sets the status bit OTUk_SM_BIP8ERRS. OTUk_SM_BIP8ERRS and its
respective interrupt mask bit, OTUk_SM_BIP8ERRM, create a maskable interrupt.
SM Backward Defect Indication (BDI) Monitor
The SM BDI monitor debounces SM BDI by detecting identical SM BDI bits over five consecutive
frames. The live bit OTUk_SM_BDIL is the last valid value of the debounced BDI. A status bit
OTUk_SM_BDIS is set on each OTUk_SM_BDIL change of state. OTUk_SM_BDIS and its respective
mask bit OTUk_SM_BDIM create a maskable interrupt.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
