VSC6134
Datasheet
When reading the 32-bit counter cache registers, the microprocessor must read the 16-bit MSB of the
count first (bits 31:16), at which time the 16-bit LSB of the count (bits 15:0) is transferred to a shadow
register. When the microprocessor reads the 16-bit LSB of the count, it is the shadow register that is
read.
Associated with the error counters are the pins RXONEERR0 and RXZEROERR0 for the line side and
RXONEERR1 and RXZEROERR1 for the client side. The respective pins toggle if the decoders correct
any bit error, a one or a zero, in a 64-bit word. Note that the definition for a 1 error and 0 error is
different between Standard FEC and Enhanced FEC modes. For Enhanced FEC modes, a 1 that is
transmitted, corrupted to a 0, and corrected to a 1 is considered a 0 error. In Standard FEC mode, the
same error is defined as a 1 error.
Setting the configuration bit FEC_DISABLE disables FEC error performance monitoring in Standard
FEC mode. (This is used for inter-working of equipment supporting FEC with equipment not supporting
FEC.) In this mode the contents of the FEC check bytes are ignored, so the FEC error counters do not
increment and the FEC error status bit is not set.
During an out-of-frame condition, the error counters discontinue accumulating errors.
2.9.4
Serial Interfaces
The VSC6134 has two pairs of serial data interfaces, one pair for the line OTUk receiver and one pair
for the client OTUk receiver, that share the same clock and frame sync signals. One interface provides
the digital wrapper overhead data and selected error statistics and the other provides the stuff column
bytes extracted from the OTUk frame.
2.9.4.1
Digital Wrapper Overhead Serial Interface
The MTC6134 transmits extracted digital wrapper overhead data and selected error statistics via a serial
interface. An FPGA interfaces to the line overhead processor and FEC performance monitor through the
pins DROPOHCLK0, RXOCHFS0, and RXOCHD0. An FPGA interfaces to the client overhead
processor and FEC performance monitor through the pins ADDOHCLK1, RXOCHFS1, and
RXOCHD1.
The error statistics reported on the serial interface have their own set of accumulators and are separate
from the error counts accessible from the microprocessor interface. The serial interface error counters
accumulate the errors over two OTUk row times.
The following figure shows the output serial interface timing. The output clock is ~55.7 MHz
(167 MHz/3). Note DROPOHCLK0 and ADDOHCLK1 are low during reset. The frame sync indicates
the beginning of the 16 overhead bytes for the first row of every OTU frame. At 55.7 MHz, the
MTC6134 can transmit 170 bits per OTU row, which allows for 16 bytes of OTU overhead and
additional proprietary status information for system use.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
