VSC6134
Datasheet
Figure 28. Receive Digital Wrapper Overhead Serial Interface Timing
DROPOHCLK
td (Delay Time)
RXOCHFS
(Frame Sync)
RXOCHD
(MSB of FAS Overhead Byte #1)
Cycle #2
Cycle #1
Cycle #680
The following table describes the RXOCHD1 and RXOCHD0 content during the 680 cycles between
frame syncs (RXOCHFS0 and RXOCHFS1).
Table 49. RXOCHD1 and RXOCHD0 Output Digital Wrapper Overhead Content
Cycle Number
1-128
Size
Description
16 bytes
4 bits
DW overhead from row #1
129-132
SM BEI. This indicates the parity errors as calculated from the received SM
BIP-8. For more information, see “BEI Transmission to the DW Overhead
Generator,” page 137.
133-144
145
12 bits
1 bit
Reserved (0x000)
Loss of frame (LOF)
146
1 bit
Out of frame (OOF)
147-158
159-170
171-298
299-302
12 bits
12 bits
16 bytes
4 bits
Corrected zero errors in the first two rows of OTU frame
Corrected one errors in the first two rows of OTU frame
DW overhead from row #2
TCM6 BEI. For more information, see “BEI Transmission to the DW
Overhead Generator,” page 137.
303-306
307-310
4 bits
4 bits
TCM5 BEI. For more information, see “BEI Transmission to the DW
Overhead Generator,” page 137.
TCM4 BEI. For more information, see “BEI Transmission to the DW
Overhead Generator,” page 137.
311-314
315
4 bits
1 bit
Reserved (0b0000)
Loss of MFAS (LOM)
316
1 bit
OTU AIS
317-328
329-340
12 bits
12 bits
Total corrected bit errors in the first two rows of OTU frame
Uncorrectable codeword count from the final 4k decoder in Enhanced FEC
mode or from the Reed Solomon decoder in Standard FEC mode, relevant to
the first two rows of OTU frame.
122 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
