VSC6134
Datasheet
2.9.5.3
ODUk Tandem Connection Monitoring (TCM)
The overhead processor always monitors all six TCM fields. Each TCM field has its own set of registers
that create six sets of identical TCM field registers. The six sets of registers, however, share the same
microprocessor address space. OTUk_TCM_INDEX[2:0] addresses each (or pages among) the six set
of registers (see the following table).
Table 51. OTUk_TCM_INDEX[2:0] Encoding
OTUk_TCM_INDEX[2:0]
Function
000
001
010
011
100
101
110
111
Reserved
TCM1 registers
TCM2 registers
TCM3 registers
TCM4 registers
TCM5 registers
TCM6 registers
Reserved
TCM TTI Monitor
The TCM TTI monitor stores the TCM TTI bytes in the stack OTUk_TCM_TTI[31:0][15:0] at
locations pointed to by MFAS. The microprocessor may point to any byte in the stack by initializing the
microprocessor stack pointer OTUk_TCM_TTIPNT[4:0]. Each microprocessor read or write to the
stack automatically increments the stack pointer. (Writes to the stack are for testing purposes only.)
The live bits OTUk_TCM_TTISAPIL (SAPI), OTUk_TCM_TTIDAPIL (DAPI), and
OTUk_TCM_TTIOPSL (operator-specific) indicate whether the respective TTI fields stored in the stack
are valid (1) or invalid (0). A change of any field state sets the respective status bit
OTUk_TCM_TTISAPIS (SAPI), OTUk_TCM_TTIDAPIS (DAPI), or OTUk_TCM_TTIOPSS
(operator-specific). The status bits with their respective interrupt mask bits OTUk_TCM_TTISAPIM
(SAPI), OTUk_TCM_TTIDAPIM (DAPI), and OTUk_TCM_TTIOPSM (operator-specific) create
maskable hardware interrupts.
A TTI trace is valid after n consecutive matches (that is, debounced n times), where n has a value of 1
through 8 and is set through register bits OTUk_TTI_MAT[2:0]. A TTI trace is invalid after m
consecutive mismatches, where m has a value of 1 through 8 and is set through register bits
OTUk_TTI_MIS[2:0].
Any one of the following conditions resets the debouncing and pauses TCM TTI monitoring:
●
●
●
●
●
●
OOF when OTUk_OOFDBC_CTRL = 1
LOF
LOS
LOM
TCM LCK
TCM OCI
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VMDS-10185 Revision 4.0
July 2006