TMC6200 DATASHEET (Rev. 1.01 / 2018-NOV-15)
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4.1.2 Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC6200 has four signals:
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SCK – bus clock input
SDI – serial data input
SDO – serial data output
CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC6200.
The TMC6200 does not allow cascading of SPI slaves. Use individual CSN lines for each device.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave.
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