TMC4361 DATASHEET (Rev. 2.68 / 2015-Apr-14) Preliminary
10
5 SPI Control Interface
The TMC4361 uses 40 bit SPI™ datagrams for communication with a microcontroller. The bit-serial
interface is synchronous to a bus clock. For every bit sent from the bus master to the bus slave,
another bit is sent simultaneously from the slave to the master. Communication between an SPI master
and the TMC4361 slave always consists of sending one 40-bit command word and receiving one 40-bit
status word. The SPI command rate typically comprises a few commands per complete motor motion.
SPI CONTROL INTERFACE
Pin Name
Type
Remarks
NSCSIN
SCKIN
SDIIN
Input
Input
Input
Output
Chip Select of the SPI-µC interface (low active)
Clock of the SPI-µC interface
Data input of the SPI-µC interface
Data output of the SPI-µC interface
SDOIN
5.1 SPI Datagram Structure
Microcontrollers which are equipped with hardware SPI are typically able to communicate using integer
multiples of 8 bit. The NSCSIN line of the TMC4361 has to be handled in a way, that it stays active (low)
for the complete duration of the datagram transmission.
Each datagram sent to the TMC4361 is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set of the TMC4361. Each register is
accessed via 32 data bits even if it uses less than 32 data bits.
Each register is specified by a one byte address:
-
-
For a read access the most significant bit of the address byte is 0.
For a write access the most significant bit of the address byte is 1.
Some registers are write only registers, most can be read additionally, and there are also some read
only registers.
TMC4361 SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
LSB (transmitted last)
39 ...
... 0
8 bit address
8 bit SPI status
39 ... 32
32 bit data
31 ... 0
to TMC4361:
RW + 7 bit address
from TMC4361:
8 bit SPI status
39 / 38 ... 32
8 bit data
31 ... 24
8 bit data
8 bit data
8 bit data
7 ... 0
23 ... 16
23...20
15 ... 8
15...12
W
38...32
31...28
27...24
19...16
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
5.1.1 Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram).
This bit is 0 for read access and 1 for write access. So, the bit named W is a WRITE_notREAD control
bit. The active high write bit is the MSB of the address byte. Thus, 0x80 has to be added to the address
for a write access. The SPI interface always delivers data back to the master, independent of the W bit.
The data transferred back is the data read from the address which was transmitted with the previous
datagram, if the previous access was a read access. If the previous access was a write access, then the
data read back mirrors the previously received write data. So, the difference between a read and a write
access is that the read access does not transfer data to the addressed register but it transfers the
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