TMC4361 DATASHEET (Rev. 2.68 / 2015-Apr-14) Preliminary
13
6 Input Filtering
Input signals can be noisy due to long cables and circuit paths. To prevent jamming, every input pin
provides a Schmitt Trigger. Additionally, several signals are passed through a digital filter. Particular
input pins are separated into four filtering groups. Each group can be programmed individually
according to its filter characteristics.
PINS AND REGISTERS: INPUT FILTERING GROUPS
Pin names
Type
Remarks
A_SCLK
B_SDI
N
Inputs
Encoder interface input pins
ANEG_NSCLK
BNEG_NSDI
NNEG
STOPL
HOME_REF
Inputs
Reference input pins
STOPR
START
Input
START input pin
SDODRV_SCLK
SDIDRV_NSCLK
STPIN
Inputs
Master clock input interface pins for serial encoder
Inputs
Step/Dir interface inputs
DIRIN
Pin name
INPUT_FILT_CONF
Register address Remarks
0x03 RW Filter configuration for all four input groups
6.1 Input Filter Configuration
Every filtering group can be configured separately with regard to input sample rate and digital filter
length.
6.1.1 Input Sample Rate (SR)
Input sample rate = fCLK ∙ 1 / 2SR
where SR (extended with the particular name extension) is in [0… 7].
This means that every (2SR)th input bit will be considered for internal processing.
Sample rate configuration
SR value
Sample rate
fCLK
fCLK / 2
fCLK / 4
fCLK / 8
fCLK / 16
fCLK / 32
fCLK / 64
fCLK / 128
0
1
2
3
4
5
6
7
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