TMC4361 DATASHEET (Rev. 2.68 / 2015-Apr-14) Preliminary
11
address only and its 32 data bits are dummies. Further, the following read or write access delivers back
data read from the address transmitted in the preceding read cycle.
ATTENTION A read access request datagram uses dummy write data. Read data is transferred back to
the master with the subsequent read or write access. Hence, reading multiple registers can be done in
a pipelined fashion. Data which will be delivered are latched immediately after the prior data transfer.
Whenever data is read from or written to the TMC4361, the MSBs delivered back contain the SPI status
SPI_STATUS, which is a number of eight status bits. The selection of these bits will be explained in
chapter 7.2.
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to be
set to 0x21 in the access preceding the read access. For a write access to the register
(VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data bit
might have any value, e.g., 0.
action
read XACTUAL
read XACTUAL
write VACTUAL:= 0x00ABCDEF
write VACTUAL:= 0x00123456
data sent to TMC…
0x2100000000
0x2100000000
0xA200ABCDEF
0xA200123456
data received from TMC…
0xSS & unused data
0xSS & X_ACTUAL
0xSS & X_ACTUAL
0xSS00ABCDEF
*)SS: is a placeholder for the status bits SPI_STATUS
5.1.2 Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values; some represent integer
values (signed) as two’s complement numbers. Single bits or groups of bits are represented as single
bits respectively as integer groups.
5.2 SPI Signals
The SPI bus on the TMC4361 has four signals:
SCKIN
SDIIN
– bus clock input
– serial data input
SDOIN – serial data output
NSCSIN – chip select input (active low)
The slave is enabled for an SPI transaction by a transition to low level on the chip select input NSCSIN.
Bit transfer is synchronous to the bus clock SCKIN, with the slave latching the data from SDIIN on the
rising edge of SCKIN and driving data to SDOIN following the falling edge. The most significant bit is
sent first. A minimum of 40 SCKIN clock cycles is required for a bus transaction with the TMC4361. If
less than 40 clock cycles are transmitted, the transfer will not be valid, even for a read access. However,
sending only eight clock cycles can be useful to obtain the SPI status because it sends the status
information back first.
If more than 40 clocks are driven, the additional bits shifted into SDIIN are shifted out on SDOIN after
a 40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
NSCSIN must be low during the whole bus transaction. When NSCSIN goes high, the contents of the
internal shift register are latched into the internal control register and recognized as a command from
the master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising
edge of NSCSIN are recognized as the command.
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