UCD8220, UCD8620
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SLUS652B–MARCH 2005–REVISED SEPTEMBER 2005
When the CS voltage is below ILIM, the driver output
follows the PWM command. The CLF digital output
flag is monitored by the host controller to determine
when a current limit event occurs, and to then apply
the appropriate algorithm to obtain the desired current
limit profile (i.e. straight line, fold back, hickup, or
latch-off).
restart the device in the event that it is not operating
properly. But these peripherals typically do not react
fast enough to save the power stage. The UCD87K’s
local current limit comparator provides the required
fast protection for the power stage.
The CS threshold is 25 mV below the ILIM voltage. If
the user attempts to command zero current while the
CS pin is at ground, the CLF flag latches high until
the CLK pin receives a pulse. At start-up, it is
necessary to ensure that the ILIM pin is always
greater than the CS pin for the handshaking to work.
If for any reason the CS pin comes to within 25 mV of
the ILIM pin during start-up, then the CLF flag is
latched high and the digital controller must poll the
UCD8620 device, by sending it a narrow CLK pulse.
If a fault condition is not present, the CLK pulse
resets the CLF signal to low indicating that the
UCD8620 device is ready to process power pulses.
A benefit of this local protection feature is that the
UCD8620 devices protects the power stage if the
software code in the digital controller becomes cor-
rupted. If the controller’s PWM output stays high, the
local current sense circuit turns off the driver output
when an overcurrent event occurs. The system then
goes into retry mode because most DSP and
microcontrollers have an on-board watchdog,
brown-out, and other supervisory peripherals to
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