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UCC28070-Q1 参数 Datasheet PDF下载

UCC28070-Q1图片预览
型号: UCC28070-Q1
PDF下载: 下载PDF文件 查看货源
内容描述: 交错连续导通模式PFC控制器 [INTERLEAVING CONTINUOUS CONDUCTION MODE PFC CONTROLLER]
分类和应用: 功率因数校正控制器
文件页数/大小: 43 页 / 883 K
品牌: TI [ TEXAS INSTRUMENTS ]
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UCC28070-Q1  
www.ti.com  
SLUSA71A JULY 2010REVISED JUNE 2011  
The multiplier output current IIMO for any line and load condition can thus be determined by the equation  
17mA´ V  
(
´ V -1  
VAO  
) (  
kVFF  
)
VINAC  
IIMO  
=
(13)  
2
Because the kVFF value represents the scaled VRMS at the center of a level, VVAO will adjust slightly upwards or  
downwards when VINACpk is either lower or higher than the center of the QVFF voltage range to compensate for  
the difference. This is automatically accomplished by the voltage loop control when VIN varies, both within a level  
and after a transition between levels.  
The output of the voltage-error amplifier VAO is clamped at 5.0 V, which represents the maximum PFC output  
power. This value is used to calculate the maximum reference current at the IMO pin, and sets a limit for the  
maximum input power allowed (and, as a consequence, limits maximum output power).  
Unlike a continuous VFF situation, where maximum input power is a fixed power at any VRMS input, the discrete  
QVFF levels permit a variation in maximum input power within limited boundaries as the input VRMS varies within  
each level.  
The lowest maximum power limit occurs at the VINAC voltage of 0.76 V, while the highest maximum power limit  
occurs at the increasing threshold from level-1 to level-2. This pattern repeats at every level transition threshold,  
keeping in mind that decreasing thresholds are 95% of the increasing threshold values. Below VINAC = 0.76 V,  
PIN is always less than PIN(max), falling linearly to zero with decreasing input voltage.  
For example, to design for the lowest maximum power allowable, determine the maximum steady-state (average)  
output power required of the PFC pre-regulator and add some additional percentage to account for line drop-out  
recovery power (to recharge COUT while full load power is drawn) such as 10% or 20% of POUT(max). Then apply  
the expected efficiency factor to find the lowest maximum input power allowable:  
1.10´ P  
OUT(max)  
P
=
IN(max)  
h
(14)  
At the PIN(max) design threshold, VVINAC = 0.76 V, hence QVFF = 0.398 and input VAC = 73 VRMS (accounting for  
2-V bridge-rectifier drop) for a nominal 400-V output system.  
P
IN(max)  
Thus IIN( rms )  
=
,and IIN( pk ) =1.414´ IIN( rms )  
73VRMS  
(15)  
Copyright © 20102011, Texas Instruments Incorporated  
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