UCC28070-Q1
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SLUSA71A –JULY 2010–REVISED JUNE 2011
VIN
L1
D1
–
+
To CSB1
RDMX
1
T1
RS1
VREF1
1
2
3
4
5
6
7
8
9
CDR
RDM
VAO
DMAX 20
RT 19
RRT1
SS 18
RA
M1
VSENSE GDB 17
VINAC
IMO
GND 16
VCC 15
12V to 21V
RB
RSYNTH GDA 14
L2
CSB1
VREF1
D2
CSB
CSA
VREF 13
CAOA 12
From Ixfrms
CSA1
To CSA1
10 PKLMT CAOB 11
T2
RS2
M2
CZV
CZC
CZC
RPK1
CREF
CPV
CPC
CPC
CSS
RPK2
VOUT
RZV
RZC
RZC
RZC
RZC
RA
COUT
CPC
CPC
RB
CREF
CZC
CZC
Vin
L3
D3
To CSA2
T3
RS3
10 PKLMT CAOB 11
CSB2
9
8
7
6
5
4
3
2
1
CSA
CSB
CAOA 12
VREF 13
From Ixfrms
CSA2
VREF2
M3
RSYNTH GDA 14
12V to 21V
IMO
VCC 15
GND 16
VINAC
VSENSE GDB 17
L4
D4
VAO
RDM
CDR
SS 18
RT 19
RRT2
To CSB2
DMAX 20
RDMX2
T4
Synchronized
Clocks
w/ 180o
Phase Shift
RS4
M4
Figure 18. Simplified Four-Phase Application Diagram Using Two UCC28070
Copyright © 2010–2011, Texas Instruments Incorporated
19
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