UCC28070-Q1
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SLUSA71A –JULY 2010–REVISED JUNE 2011
Enhanced Transient Response (VA Slew-Rate Correction)
Due to the low voltage loop bandwidth required to maintain proper PFC and ignore the slight 120-Hz ripple on
the output, the response of ordinary controllers to input voltage and load transients will also be slow. However,
the QVFF function effectively handles the line transient response with the exception of any minor adjustments
needed within a QVFF level. Load transients on the other hand can only be handled by the voltage loop, therefore,
the UCC28070 has been designed to improve its transient response by pulling up on the output of the voltage
amplifier (VAO) with an additional 100 μA of current in the event the VSENSE voltage drops below 93% of
regulation (2.79 V). During a soft-start cycle, when VSENSE is ramping up from the 0.75-V PFC Enable
threshold, the 100-μA correction current source is disabled to ensure the gradual and controlled ramping of
output voltage and current during a soft start.
Voltage Biasing (VCC and VREF)
The UCC28070 operates within a VCC bias supply range of 10 V to 21 V. An Under-Voltage Lock-Out (UVLO)
threshold prevents the PFC from activating until VCC > 10.2 V, and 1 V of hysteresis assures reliable start-up
from a possibly low-compliance bias source. An internal 25-V zener-like clamp on VCC is intended only to protect
the device from brief energy-limited surges from the bias supply, and should NOT be used as a regulator with a
current-limited source.
At minimum, a 0.1-μF ceramic bypass capacitor must be applied from VCC to GND close to the device pins to
provide local filtering of the bias supply. Larger values may be required depending on ICC peak current
magnitudes and durations to minimize ripple voltage on VCC.
In order to provide a smooth transition out of UVLO and to make the 6-V voltage reference available as early as
possible, the VREF output is enabled when VCC exceeds 8 V typically.
The VREF circuitry is designed to provide the biasing of all internal control circuits and for limited use externally.
At minimum, a 22-nF ceramic bypass capacitor must be applied from VREF to GND close to the device pins to
ensure stability of the circuit. External load current on VREF should be limited to less than 2 mA, or degraded
regulation may result.
PFC Enable and Disable
The UCC28070 contains two independent circuits dedicated to disabling the GDx outputs based on the biasing
conditions of the VSENSE or SS pins. The first circuit which monitors the VVSENSE, is the traditional PFC Enable
that holds off soft-start and the overall PFC function until the output has pre-charged to ~25%. Prior to VVSENSE
reaching 0.75 V, almost all of the internal circuitry is disabled. Once VVSENSE reaches 0.75 V and VAO < 0.75 V,
the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage
on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable
the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6
V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present,
normal PWM operation resumes when the external SS pulldown is released. It must be noted that the external
pulldown needs to be sized large enough to override the internal 1.5-mA adaptive SS pullup once the SS voltage
falls below the disable threshold. It is recommended that a MOSFET with less than 100-Ω RDS(on) resistance be
used to ensure the SS pin is held adequately below the disable threshold.
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