UCC28070-Q1
www.ti.com
SLUSA71A –JULY 2010–REVISED JUNE 2011
Programmable Peak Current Limit
The UCC28070 has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling
either GDA or GDB output whenever the corresponding current-sense input (CSA or CSB respectively) rises
above the voltage established on the PKLMT pin. Once an output has been disabled via the detection of peak
current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming
range of the PKLMT voltage extends to upwards of 4 V to permit the full utilization of the 3-V average current
sense signal range, however it should be noted that the linearity of the current amplifiers begin to compress
above 3.6 V.
A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT,
provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage. A load of
less than 0.5 mA is suggested, but if the resistance on PKLMT is very high, a small filter capacitor on PKLMT is
recommended to avoid operational problems in high-noise environments.
PKLMT
Externally Programmable Peak
Current Limit level (PKLMT)
10
IPEAKx
To Gate-Drive
Shut-down
+
CSx
Current
Synthesizer
To Current
Amplifier
DI
3V Average Current-sense
Signal Range, plus Ripple
Figure 20. Externally Programmable Peak Current Limit
Copyright © 2010–2011, Texas Instruments Incorporated
21
TI [ TEXAS INSTRUMENTS ]
