UCC28070-Q1
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SLUSA71A –JULY 2010–REVISED JUNE 2011
External Clock Synchronization
The UCC28070 has also been designed to be easily synchronized to almost any external frequency source. By
disabling frequency dithering (pulling CDR > 5 V), the UCC28070's SYNC circuitry is enabled permitting the
internal oscillator to be synchronized with pulses presented on the RDM pin. In order to ensure a precise 180
degree phase shift is maintained between the GDA and GDB outputs, the frequency (fSYNC) of the pulses
presented at the RDM pin needs to be at twice the desired fPWM. For example, if a 100-kHz switching frequency
is desired, the fSYNC should be 200 kHz.
fSYNC
fPWM
=
2
(7)
In order to ensure the internal oscillator does not interfere with the SYNC function, RRT should be sized to set the
internal oscillator frequency at least 10% below the fSYNC
.
15000
R kW =
RT ( )
´1.1
f
kHz
SYNC ( )
(8)
It must be noted that the PWM modulator gain will be reduced by a factor equivalent to the scaled RRT due to a
direct correlation between the PWM ramp current and RRT. Adjustments to the current loop gains should be
made accordingly.
It must also be noted that the maximum duty cycle clamp programmability is affected during external
synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the
falling edge of the synchronization pulse. Therefore, the selection of RDMX becomes dependent on the
synchronization pulse width (tSYNC).
DSYNC = tSYNC ´ fSYNC
(9)
For use in RDMX equation immediately below.
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ç
è
ö
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15000
R
kW =
DMX ( )
´ 2´ D
(
-1- DSYNC
)
MAX
fSYNC ( kHz )
(10)
Consequently to minimize the impact of the tSYNC it is clearly advantageous to utilize the smallest synchronization
pulse width feasible.
NOTE
When external synchronization is used, a propagation delay of approximately 50 ns to 100
ns exists between internal timing circuits and the SYNC signal's falling edge, which may
result in reduced off-time at the highest of switching frequencies. Therefore, RDMX should
be adjusted downward slightly by (TSYNC-0.1 μs)/TSYNC to compensate. At lower SYNC
frequencies, this delay becomes an insignificant fraction of the PWM period, and can be
neglected.
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