TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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6.7 I2C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
1.3
0
TYP
MAX
UNIT
µs
t1
Bus free time between STOP and START
Data hold time
t2
0.9
µs
t3
Data setup time
100
0.6
0.6
0.6
ns
t4
Setup time for a (repeated) START condition
Setup time for a STOP condition
Hold time (repeated) START condition
Rise time VC1(SDA) and VC0(SCL) signal
Fall time VC1(SDA) and VC0(SCL) signal
Capacitive load for each bus line
I2C clock frequency
µs
t5
µs
t6
µs
t7
specified by design(1)
specified by design(1)
specified by design(1)
250
250
400
400
ns
t8
ns
Cb
f12C
pF
kHz
(1) Assured by design. Not tested.
t
2
t
t
t
3
4
1
90%
10%
SCLK
t
5
t
6
90%
10%
Y, C, AVID,
Valid Data
Valid Data
VS, HS, FID
Figure 6-1. Clocks, Video Data, and Sync Timing
Stop Start
Stop
VC1 (SDA)
VC0 (SCL)
Data
t
t
1
6
t
3
t
6
t
2
t
5
t
4
t
t
7
8
Change
Data
Figure 6-2. I2C Host Port Timing
100
Electrical Specifications
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