TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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6.9 Example SDRAM Timing Alignment
Samsung K4S161622E-80, CAS latency = 3, Clock delay = 0 ns
t
= 9.2 ns
t
= 1.1 ns
= 0.3 ns
1
6
t
= 4.6 ns
t
2
7
2.5 ns
SDRAM_CLK
Address/Data_out
Data_in
9.2 ns
6 ns
2.5 ns
1 ns
2.5 ns
1 ns
4.6 ns
2 ns
SDRAM_CLK_out
Address/Data_in
Data_out
SDRAM-K4S161622E-80 (CAS LAT = 3)
t
t
(dhm)
(dsum)
Data = read margin
t
t
= 9.2 - 6 - 1.1 ns = 2.1 ns
(dsum)
= 2.5 - 0.3 ns = 2.2 ns
(dhm)
Figure 6-4. TVP5160 Timing Relationship with K4S161622E-80 SDRAM
102
Electrical Specifications
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