TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
6.8 SDRAM Timing(1)
CL = 10 pF, CAS latency = 3, Clock delay = 0 ns
PARAMETER
TEST CONDITIONS
MIN
TYP
9.2
4.6
4.6
MAX
UNIT
ns
t1
t2
t3
t4
t5
t6
t7
t8
tg
Clock period (108 MHz)
Clock high period
ns
Clock low period
ns
Clock to output valid time (address/data/control)
Output hold time
5.3
ns
1.8
1.1
0.3
ns
Data in setup time
ns
Data in hold time
ns
Clock rise time, 10% to 90%
Clock fall time, 90% to 10%
4
4
ns
ns
(1) Assured by design. Not tested.
t
t
6
t
1
4
t
t
t
t
7
2
3
5
SDRAM_CLK
Address/Control
Data_out
Data_in
Figure 6-3. SDRAM Interface Timing
Copyright © 2005–2011, Texas Instruments Incorporated
Electrical Specifications
101
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