TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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5
Typical Register Programming Sequence
Composite Input, Autoswitch, 10-bit ITU-656, 3DYC and 3DNR Enabled
// Address, Data
0xEE, 0x01 // ROM Initialization Procedure - Required
0xEA, 0xB0
0xE9, 0x00
0xE8, 0x63
0xE0, 0x01
0xEE, 0x00
0x00, 0x00 // Input/Output Select - Composite input selected (default)
0x06, 0x40 // Luminance Processing Control 1 - No pedestal present
0x33, 0x40 // Output Formatter Control 1 - 10-bit ITU-656 (default)
0x34, 0x11 // Output Formatter Control 2 - Data and SCLK enabled
0x35, 0x2A // Output Formatter Control 3 - GPIO (pin 82) = 0, GLCO, AVID, and FID enabled
0x36, 0xAF // Output Formatter Control 4 - HS and VS enabled
0x59, 0x07 // SDRAM Control - 64-Mbit SDRAM configured and enabled; must be set before enabling
3DYC
or 3DNR
0x0D, 0x84 // Chrominance Processing Control 1 - 3DYC and 3DNR enabled
480p Progressive Inputs, Autoswitch, 20-bit ITU-656, 3DYC and 3DNR Enabled
// Address, Data
0xEE, 0x01 // ROM Initialization Procedure - Required
0xEA, 0xB0
0xE9, 0x00
0xE8, 0x63
0xE0, 0x01
0xEE, 0x00
0x00, 0x95 // Input/Output Select - Y(VI_5), Pb(VI_11), Pr(VI_8)
0x06, 0x40 // Luminance Processing Control 1 - No pedestal present
0x30, 0x0F // Component Autoswitch Mask - 480i/p and 576i/p enabled in autoswitch
0x33, 0x44 // Output Formatter Control 1 - 20-bit ITU-656
0x34, 0x11 // Output Formatter Control 2 - Data and SCLK enabled
0x35, 0x2A // Output Formatter Control 3 - GPIO (pin 82) = 0, GLCO, AVID, and FID are enabled
0x36, 0xAF // Output Formatter Control 4 - HS and VS enabled
0x59, 0x07 // SDRAM Control - 64-Mbit SDRAM configured and enabled; must be set before enabling
3DYC
or 3DNR
0x0D, 0x84 // Chrominance Processing Control 1 - 3DYC and 3DNR enabled
96
Typical Register Programming Sequence
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