TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
6.5 Analog Processing and A/D Converters
FS = 60 MSPS for CH1, CH2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kΩ
pF
Zi
Input impedance, analog video inputs
Input capacitance, analog video inputs
Input voltage range
specified by design (not tested)
specified by design (not tested)
Ccoupling = 0.1 µF
200
Ci
Vi(PP)
ΔG
0.50
–6.7
–7.5%
2
1.0
V
Input gain control range
Input gain ratio, N = 0 to 15
Input offset control per step
Absolute differential nonlinearity
Absolute integral nonlinearity
Frequency response
dB
0.5 +N/10
4
0.75
1
LSB
LSB
LSB
dB
DNL
INL
AFE only
AFE only
FR
Multiburst (60 IRE)
1 MHz
–0.9
XTALK
SNR
GM
Crosstalk
dB
Signal-to-noise ratio all channels
Gain match(1)
FIN = 1 MHz, 1.0 VPP
Full scale, 1 MHz
54
dB
1.5
%
Luma ramp
(100 kHz to full, tilt null)
NS
Noise spectrum
–58
dB
DP
DG
Differential phase
Modulated ramp
Modulated ramp
0.5
°
Differential gain
±1.5
%
%
Analog output gain ratio, N = 0 to 15
–8% 1.3 + 0.26xN
8
(1) Component inputs only
6.6 Data Clock, Video Data, Sync Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
%
Duty cycle SCLK
45
55
t1
t1
t1
t2
t2
t2
t3
t4
t5
t6
High time, SCLK @ 13.5 MHz
High time, SCLK @ 27 MHz
High time, SCLK @ 54 MHz
Low time, SCLK @ 13.5 MHz
Low time, SCLK @ 27 MHz
Low time, SCLK @ 54 MHz
Fall time, SCLK
≥ 50%
37
ns
≥ 50%
18.5
9.25
37
≥ 50%
≤ 50%
ns
≤ 50%
18.5
9.25
≤ 50%
90% to 10%
10% to 90%
To 90%/10%
To 90%/10%
5
5
5
ns
ns
ns
ns
Rise time, SCLK
Data valid time
Data hold time
2.5
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Electrical Specifications
99
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