TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N –MARCH 2010–REVISED APRIL 2012
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Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
(1)
3:2
1:0
SEL
ST
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.5 V
SEL[1:0] = 10 : 2.8 V
SEL[1:0] = 11 : 2.85 V
RW
See
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
RW
0x0
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 54. VAUX2_REG
Address Offset
Physical Address
Description
Type
0x33
Instance
VAUX2 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
(1)
3:2
1:0
SEL
Supply voltage (EEPROM bits):
SEL[1:0] = 00 : 1.8 V
SEL[1:0] = 01 : 2.8 V
SEL[1:0] = 10 : 2.9 V
SEL[1:0] = 11 : 3.3 V
RW
See
ST
Supply state (EEPROM bits):
ST[1:0] = 00 : Off
RW
0x0
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)
(1) The reset value for this field varies with boot mode selection and the processor support. Please refer to the corresponding processor
user guide to find the correct default value.
Table 55. VAUX33_REG
Address Offset
Physical Address
Description
Type
0x34
Instance
VAUX33 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
70
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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