TPS54531
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SLVSBI5 –MAY 2013
OUTPUT VOLTAGE SET POINT
The output voltage of the TPS54531 is externally adjustable using a resistor divider network. In the application
circuit of Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 4 and Equation 5:
R5 ´ VREF
R6 =
VOUT - VREF
(4)
R5
é
ù
VOUT = VREF
´
+1
ê
ú
R6
ë
û
(5)
Choose R5 to be approximately 10.0 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resistors. In this design, R5 = 10.2 kΩ and R6 = 1.96 kΩ, resulting in a 4.96
V output voltage. The 51.1 ohm resistor R4 is provided as a convenient place to break the control loop for
stability testing.
Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R1 and R2.
R1 is connected between VIN and the EN pin of the TPS54531 and R2 is connected between EN and GND .
The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or
brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the
start voltage threshold is set to 7 V with 2 V hysteresis. Equation 1 and Equation 2 can be used to calculate the
values for the upper and lower resistor values of R1 and R2.
INPUT CAPACITORS
The TPS54531 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54531 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design two 4.7 μF capacitors are used for the input decoupling capacitor. They are
X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2mΩ, and the current
rating is 3 A. Additionally, a small 0.01 μF capacitor is included for high frequency filtering.
This input ripple voltage can be approximated by Equation 6
IOUT(MAX) ´ 0.25
DV
=
+ IOUT(MAX) ´ ESRMAX
(
)
IN
CBULK ´ fSW
(6)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value
and ESRMAX is the maximum series resistance of the bulk capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 7
IOUT(MAX)
ICIN
=
2
(7)
In this case, the input ripple voltage would be 243 mV and the RMS ripple current would be 2.5 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Design Parameters and is larger than the calculated value. This measured value is still below the specified input
limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen
bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both
providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded
under any circumstance.
Copyright © 2013, Texas Instruments Incorporated
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