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TPS51640ARSLR 参数 Datasheet PDF下载

TPS51640ARSLR图片预览
型号: TPS51640ARSLR
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道( 3相CPU / 1相GPU) SVID , D- CAP + ™降压控制器 [Dual-Channel (3-Phase CPU/1-Phase GPU) SVID, D-CAP+? Step-Down Controller for]
分类和应用: 控制器
文件页数/大小: 54 页 / 1760 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TPS51640ARSLR的Datasheet PDF文件第29页浏览型号TPS51640ARSLR的Datasheet PDF文件第30页浏览型号TPS51640ARSLR的Datasheet PDF文件第31页浏览型号TPS51640ARSLR的Datasheet PDF文件第32页浏览型号TPS51640ARSLR的Datasheet PDF文件第34页浏览型号TPS51640ARSLR的Datasheet PDF文件第35页浏览型号TPS51640ARSLR的Datasheet PDF文件第36页浏览型号TPS51640ARSLR的Datasheet PDF文件第37页  
TPS51640A, TPS59640, TPS59641  
www.ti.com  
SLUSAQ2 JANUARY 2012  
The CPU operates in the maximum phase mode when it is in PS0. This means when the CPU channel of the  
controller is configured as 3-phase, all 3 phases are active in PS0. When configured in 2-phase mode, the two  
phases are active in PS0. But in PS1, PS2 and PS3, the operation is in single-phase mode. Additionally, the  
CPU channel in PS0 mode operates in forced continuous conduction mode (FCCM). But in PS1, PS2 and PS3,  
the CPU channel operates in diode emulation (DE) mode for additional power savings and higher efficiency.  
The single-phase GPU section always operates in diode emulation (DE) mode in all PS states.  
The slew rate for a SetVID-Fast is the slew rate set at the SLEWA pin. This slew rate is defined in the  
ELECTRICAL CHARACTERISTICS table. The SetVID-Slow is ¼ of the SetVID-Fast slew rate. On a  
SetVID-Decay the output voltage decays by the rate of the load current or 1/8 of the slew rate whichever is  
slower.  
Additionally, on a SetVID-Fast change for a VID-up transition, the gain of the gM amplifier is increased to speed  
up the response of the output voltage to meet the Intel timing requirement. So, it is possible to observe an  
overshoot at the output voltage on a VID-up transition. This overshoot is allowed by the Intel specification.  
XXX  
Table 4. VID (continued)  
Table 4. VID  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
40  
41  
42  
0.405  
0.410  
0.415  
0.420  
0.425  
0.430  
0.435  
0.440  
0.445  
0.450  
0.455  
0.460  
0.465  
0.470  
0.475  
0.480  
0.485  
0.490  
0.495  
0.500  
0.505  
0.510  
0.515  
0.520  
0.525  
0.530  
0.535  
0.540  
0.545  
0.550  
0.555  
0.560  
0.565  
0.570  
0.575  
VID VID VID VID VID VID VID VID  
HEX VDAC  
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
0.000  
0.250  
0.255  
0.260  
0.265  
0.270  
0.275  
0.280  
0.285  
0.290  
0.295  
0.300  
0.305  
0.310  
0.315  
0.320  
0.325  
0.330  
0.335  
0.340  
0.345  
0.350  
0.355  
0.360  
0.365  
0.370  
0.375  
0.380  
0.385  
0.390  
0.395  
0.400  
Copyright © 2012, Texas Instruments Incorporated  
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