TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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Table 6-11. Reset (XRS) Timing Requirements
MIN
32 tc(OSCCLK)
32 tc(OSCCLK)
NOM
MAX
UNIT
cycles
cycles
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable input clock to XRS high
Pulse duration, XRS low
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
512tc(OSCCLK)
cycles
td(EX)
tOSCST
th(boot-mode)
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
1
Hold time for boot-mode pins
200tc(OSCCLK)
cycles
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
130
Electrical Specifications
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